Hi Bjorn On Mon, Jun 29, 2020 at 02:33:16PM -0500, Bjorn Helgaas wrote: > [+cc Ashok, Ding, Casey] > > On Mon, Jun 29, 2020 at 12:32:44PM +0300, Aya Levin wrote: > > I wanted to turn on RO on the ETH driver based on > > pcie_relaxed_ordering_enabled(). > > From my experiments I see that pcie_relaxed_ordering_enabled() return true > > on Intel(R) Xeon(R) CPU E5-2650 v3 @ 2.30GHz. This CPU is from Haswell > > series which is known to have bug in RO implementation. In this case, I > > expected pcie_relaxed_ordering_enabled() to return false, shouldn't it? > > Is there an erratum for this? How do we know this device has a bug > in relaxed ordering? https://software.intel.com/content/www/us/en/develop/download/intel-64-and-ia-32-architectures-optimization-reference-manual.html For some reason they weren't documented in the errata, but under Optimization manual :-) Table 3-7. Intel Processor CPU RP Device IDs for Processors Optimizing PCIe Performance Processor CPU RP Device IDs Intel Xeon processors based on Broadwell microarchitecture 6F01H-6F0EH Intel Xeon processors based on Haswell microarchitecture 2F01H-2F0EH These are the two that were listed in the manual. drivers/pci/quirks.c also has an eloborate list of root ports where relaxed_ordering is disabled. Did you check if its not already covered here? Send lspci if its not already covered by this table. > > > In addition, we are worried about future bugs in new CPUs which may result > > in performance degradation while using RO, as long as the function > > pcie_relaxed_ordering_enabled() will return true for these CPUs. > > I'm worried about this too. I do not want to add a Device ID to the > quirk_relaxedordering_disable() list for every new Intel CPU. That's > a huge hassle and creates a real problem for old kernels running on > those new CPUs, because things might work "most of the time" but not > always. I'll check when this is fixed, i was told newer ones should work properly. But I'll confirm.
