On Tue, Jun 16, 2020 at 04:55:13PM -0400, Jim Quinlan wrote:
> From: Jim Quinlan <jquinlan@xxxxxxxxxxxx>
>
> The PERST bit was moved to a different register in 7278-type STB chips. In
> addition, the polarity of the bit was also changed; for other chips writing
> a 1 specified assert; for 7278-type chips, writing a 0 specifies assert.
>
> Signal-wise, PERST is an asserted-low signal.
s/PERST/PERST#/ to match usage of the signal name in spec.
The PERST bit above is the name of a register bit, so use whatever
matches the STB spec.
> Signed-off-by: Jim Quinlan <jquinlan@xxxxxxxxxxxx>
> Acked-by: Florian Fainelli <f.fainelli@xxxxxxxxx>
> ---
> drivers/pci/controller/pcie-brcmstb.c | 14 +++++++++++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> index 7c148eb65170..d0e256d8578a 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -83,6 +83,7 @@
>
> #define PCIE_MISC_PCIE_CTRL 0x4064
> #define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
> +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
>
> #define PCIE_MISC_PCIE_STATUS 0x4068
> #define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
> @@ -685,9 +686,16 @@ static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie, u32 val)
> {
> u32 tmp;
>
> - tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
> - u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK);
> - writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
> + if (pcie->type == BCM7278) {
> + /* Perst bit has moved and assert value is 0 */
s/Perst/PERST/ or PERST# so it doesn't look like an English word and
to match the STB spec.
> + tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL);
> + u32p_replace_bits(&tmp, !val, PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK);
> + writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL);
> + } else {
> + tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
> + u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK);
> + writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
> + }
> }
>
> static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
> --
> 2.17.1
>
