On 6/3/2020 12:20 PM, Jim Quinlan wrote: > BrcmSTB PCIe controllers are intimately connected to the memory > controller(s) on the SOC. There is a "viewport" for each memory controller > that allows inbound accesses to CPU memory. Each viewport's size must be > set to a power of two, and that size must be equal to or larger than the > amount of memory each controller supports. > > Signed-off-by: Jim Quinlan <james.quinlan@xxxxxxxxxxxx> Acked-by: Florian Fainelli <f.fainelli@xxxxxxxxx> -- Florian
