Hi Bjorn
I was trying to fix pcie_write_mrrs() since its seems to not follow PCIe
SIG recommendations.
It appears to that 010 (512b) is the default and 4096b is the max spec
allowed limit.
Current code seems to match MRRS and MPS, which seem to be completely
different purposes.
But trying to fix i got confused with all these pcie_bus_config_types.
enum pcie_bus_config_types {
PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
};
Not sure what the difference between BUS_TUNE_OFF and BUS_DEFAULT is.
MPS matching upstream bridge is required in all cases right?
BUS_SAFE/BUS_PERFORMANCE? Not sure why that is special for BUS_DEFAULT.
Wouldn't it be simple to say:
BUS_DEFAULT : Just use BIOS settings, no change to anything.
BUS_SAFE: Says Choose largest MPS boot-time settings? What does that
actually mean? Why isn't that BUS_PERFORMANCE?
P2P: Choose smallest setting makes sense.
I think only 3 settings make sense.
BUS_DEFAULT == TUNE_OFF : Choose BIOS values, don't touch anything
BUS_SAFE == BUS_PERFORMANCE : Should actually be the default.
BUS_PEER2PEER - Same as now
Do we really have value for the other settings? Maybe for BUS_DEFAULT we
should call it BUS_BIOS (to indicate real meaning)
BUS_PERFORMANCE should be the default setting for the system.
BUS_P2P if someone needs to configure for p2p.
Cheers,
Ashok
