Hi Lorenzo, RobH On 5/6/2020 8:44 PM, Kishon Vijay Abraham I wrote: > TI's J721E SoC uses Cadence PCIe core to implement both RC mode > and EP mode. > > The high level features are: > *) Supports Legacy, MSI and MSI-X interrupt > *) Supports upto GEN4 speed mode > *) Supports SR-IOV > *) Supports multiple physical function > *) Ability to route all transactions via SMMU > > This patch series > *) Add support in Cadence PCIe core to be used for TI's J721E SoC > *) Add a driver for J721E PCIe wrapper Do you have any other comments on this series? I'm hoping this gets merged for 5.8. Thanks Kishon > > v1 of the series can be found @ [1] > v2 of the series can be found @ [2] > v3 of the series can be found @ [5] > > Changes from v3: > 1) Changed the order of files in MAINTAINTERS file to fix Joe's comments > 2) Fixed indentation and added Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > 3) Cleaned up computing msix_tbl > 4) Fixed RobH's comment on J721E driver > > Changes from v2: > 1) Converting Cadence binding to YAML schema was done as a > separate series [3] & [4]. [3] is merged and [4] is > pending. > 2) Included MSI-X support in this series > 3) Added link down interrupt handling (only error message) > 4) Rebased to latest 5.7-rc1 > 5) Adapted TI J721E binding to [3] & [4] > > Changes from v1: > 1) Added DT schemas cdns-pcie-host.yaml, cdns-pcie-ep.yaml and > cdns-pcie.yaml for Cadence PCIe core and included it in > TI's PCIe DT schema. > 2) Added cpu_addr_fixup() for Cadence Platform driver. > 3) Fixed subject/description/renamed functions as commented by > Andrew Murray. > > [1] -> http://lore.kernel.org/r/20191209092147.22901-1-kishon@xxxxxx > [2] -> http://lore.kernel.org/r/20200106102058.19183-1-kishon@xxxxxx > [3] -> http://lore.kernel.org/r/20200305103017.16706-1-kishon@xxxxxx > [4] -> http://lore.kernel.org/r/20200417114322.31111-1-kishon@xxxxxx > [5] -> http://lore.kernel.org/r/20200417125753.13021-1-kishon@xxxxxx > > Alan Douglas (1): > PCI: cadence: Add MSI-X support to Endpoint driver > > Kishon Vijay Abraham I (13): > PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path > linux/kernel.h: Add PTR_ALIGN_DOWN macro > PCI: cadence: Add support to use custom read and write accessors > PCI: cadence: Add support to start link and verify link status > PCI: cadence: Add read/write accessors to perform only 32-bit accesses > PCI: cadence: Allow pci_host_bridge to have custom pci_ops > PCI: cadence: Add new *ops* for CPU addr fixup > PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register > dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC > dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC > PCI: j721e: Add TI J721E PCIe driver > misc: pci_endpoint_test: Add J721E in pci_device_id table > MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe > > .../bindings/pci/ti,j721e-pci-ep.yaml | 89 ++++ > .../bindings/pci/ti,j721e-pci-host.yaml | 113 ++++ > MAINTAINERS | 4 +- > drivers/misc/pci_endpoint_test.c | 9 + > drivers/pci/controller/cadence/Kconfig | 23 + > drivers/pci/controller/cadence/Makefile | 1 + > drivers/pci/controller/cadence/pci-j721e.c | 492 ++++++++++++++++++ > .../pci/controller/cadence/pcie-cadence-ep.c | 125 ++++- > .../controller/cadence/pcie-cadence-host.c | 59 ++- > .../controller/cadence/pcie-cadence-plat.c | 13 + > drivers/pci/controller/cadence/pcie-cadence.c | 48 +- > drivers/pci/controller/cadence/pcie-cadence.h | 158 +++++- > include/linux/kernel.h | 1 + > 13 files changed, 1093 insertions(+), 42 deletions(-) > create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml > create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml > create mode 100644 drivers/pci/controller/cadence/pci-j721e.c >
