This series adds PCIe endpoint controller driver for Socionext UniPhier
SoCs. This controller is based on the DesignWare PCIe core.
This driver supports Pro5 SoC only, so Pro5 needs multiple clocks and
resets in devicetree node.
Changes since v3:
- dt-bindings: Convert with dt-schema
- Replace with devm_platform_ioremap_resource()
- Add a commnet that mutex covers raising legacy IRQ
Changes since v2:
- dt-bindings: Add clock-names, reset-names, and fix example for Pro5
- Remove 'is_legacy' indicating that the compatible is for legacy SoC
- Use pci_epc_features instead of defining uniphier_soc_data
- Remove redundant register read access
- Clean up return code on uniphier_add_pcie_ep()
- typo: intx -> INTx
Changes since v1:
- dt-bindings: Add Reviewed-by line
- Fix register value to set EP mode
- Add error message when failed to get phy
- Replace INTx assertion time with macro
Kunihiko Hayashi (2):
dt-bindings: PCI: Add UniPhier PCIe endpoint controller description
PCI: uniphier: Add Socionext UniPhier Pro5 PCIe endpoint controller
driver
.../bindings/pci/socionext,uniphier-pcie-ep.yaml | 92 +++++
MAINTAINERS | 4 +-
drivers/pci/controller/dwc/Kconfig | 13 +-
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pcie-uniphier-ep.c | 383 +++++++++++++++++++++
5 files changed, 489 insertions(+), 4 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
create mode 100644 drivers/pci/controller/dwc/pcie-uniphier-ep.c
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2.7.4
