On Wed, May 06, 2020 at 04:29:47PM -0500, Bjorn Helgaas wrote: > On Wed, May 06, 2020 at 09:14:38AM +0300, Mika Westerberg wrote: > > On Wed, May 06, 2020 at 01:34:21AM +0800, Kai-Heng Feng wrote: > > > The TI PCIe-to-PCI bridge prevents the Intel SoC from entering power > > > state deeper than PC3 due to disabled ASPM, consumes lots of unnecessary > > > power. On Windows ASPM L1 is enabled on the device and its upstream > > > bridge, so it can make the Intel SoC reach PC8 or PC10 to save lots of > > > power. > > > > > > In short, ASPM always gets disabled on bridge-to-bridge link. > > > > Excelent finding :) I've heard several reports complaining that we can't > > enter PC10 when TBT is enabled and I guess this explains it. > > I'm curious about this. I first read this patch as affecting > garden-variety Links between a Root Port or Downstream Port and the > Upstream Port of a switch. But the case we're talking about is > specifically when the downstream device is PCI_EXP_TYPE_PCI_BRIDGE, > i.e., a PCIe to PCI/PCI-X bridge, not a switch. > > AFAICT, a Link to a PCI bridge is still a normal Link and ASPM should > still work. I'm sort of surprised that you'd find such a PCIe to > PCI/PCI-X bridge in a Thunderbolt topology, but maybe that's a common > thing? It actually is not common and now that you mention I'm wondering how this can help at all. I also thought this applies to all ports which would explain the issue we have but if it only applies to PCIe to PCI/PCI-X bridge it should not make any difference in TBT systems. > I guess "PC8" and "PC10" are some sort of Intel-specific power states? Package C-state 8 and Package C-state 10. These are power states the whole (Intel) CPU package can enter when individual CPU cores are in correct low power states.
