On 20 Apr 2020, at 15:14, Sean V Kelley wrote:
Changes since v5 [1]:
- There can be multiple vendor specific DVSEC IDs associated with CXL.
(Bjorn Helgaas)
[1]
https://lore.kernel.org/linux-pci/20200415004751.2103963-1-sean.v.kelley@xxxxxxxxxxxxxxx/
This patch series adds support for basic lspci decode of Compute
eXpress Link[2],
a new CPU interconnect building upon PCIe. As a foundation for the CXL
support it adds separate Designated Vendor-Specific Capability (DVSEC)
defines
and a cap function so as to align with PCIe r5.0, sec 7.9.6.2 terms
and
provide available details. It makes use of the DVSEC Vendor ID and
DVSEC ID so as
to identify a CXL capable device.
[2] https://www.computeexpresslink.org/
Just a light ping on these patches.
Thanks!
Sean
Sean V Kelley (2):
pciutils: Decode available DVSEC details
pciutils: Decode Compute eXpress Link DVSEC
lib/header.h | 24 ++++
ls-ecaps.c | 79 +++++++++-
tests/cap-dvsec | 340
++++++++++++++++++++++++++++++++++++++++++++
tests/cap-dvsec-cxl | 340
++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 782 insertions(+), 1 deletion(-)
create mode 100644 tests/cap-dvsec
create mode 100644 tests/cap-dvsec-cxl
--
2.26.0
