The value of PCIBIOS_MIN_MEM reported by BIOS 1.3 on Supermicro H11SSL-i
via e820__setup_pci_gap():
[mem 0xebff1000-0xfe9fffff] available for PCI devices
is only suitable for a single root complex out of four (0000:00):
pci_bus 0000:00: root bus resource [mem 0xec000000-0xefffffff window]
pci_bus 0000:20: root bus resource [mem 0xeb800000-0xebefffff window]
pci_bus 0000:40: root bus resource [mem 0xeb200000-0xeb5fffff window]
pci_bus 0000:60: root bus resource [mem 0xe8b00000-0xeaffffff window]
That makes the AMD EPYC 7251 unable to assign BARs of devices hot-added in
those three unlucky RCs (0000:20, 0000:40 and 0000:60).
If there are apertures that end below the current PCIBIOS_MIN_MEM (which is
a variable pci_mem_start on x86), adjust it to the aperture's start.
CC: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
Signed-off-by: Sergei Miroshnichenko <s.miroshnichenko@xxxxxxxxx>
---
arch/x86/pci/acpi.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
index 948656069cdd..9eccb26d0bf3 100644
--- a/arch/x86/pci/acpi.c
+++ b/arch/x86/pci/acpi.c
@@ -299,6 +299,21 @@ static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci)
int status;
status = acpi_pci_probe_root_resources(ci);
+
+ resource_list_for_each_entry(entry, &ci->resources) {
+ struct resource *res = entry->res;
+
+ if (!(res->flags & IORESOURCE_MEM) ||
+ res->end > pci_mem_start ||
+ res->start == 0xa0000)
+ continue;
+
+ dev_warn(&ci->root->device->dev, "Fix up PCI start address: %lx -> %llx\n",
+ pci_mem_start, res->start);
+
+ pci_mem_start = res->start;
+ }
+
if (pci_use_crs) {
resource_list_for_each_entry_safe(entry, tmp, &ci->resources)
if (resource_is_pcicfg_ioport(entry->res))
--
2.24.1
