Changes since v3 [1]: - Non-functional changes, subject and typo corrections Changes since v2 [2]: - Separate DVSEC capabilities from CXL and provide a means to identify. (Bjorn Helgaas) Changes since v1 [3]: - Use consistent syntax to match other lspci capability output. (Bjorn Helgaas) [1] https://lore.kernel.org/linux-pci/20200410232440.668057-1-sean.v.kelley@xxxxxxxxxxxxxxx/ [2] https://lore.kernel.org/linux-pci/20200409213019.335678-1-sean.v.kelley@xxxxxxxxxxxxxxx/ [3] https://lore.kernel.org/linux-pci/20200409183204.328057-1-sean.v.kelley@xxxxxxxxxxxxxxx/ This patch series adds support for basic lspci decode of Compute eXpress Link[4], a new CPU interconnect building upon PCIe. As a foundation for the CXL support it adds separate Designated Vendor-Specific Capability (DVSEC) defines and a cap function so as to align with PCIe r5.0, sec 7.9.6.2 terms and provide available details. It makes use of the Vendor ID so as to identify a Flex Bus capable port for purposes of CXL support. [4] https://www.computeexpresslink.org/ Sean V Kelley (2): pciutils: Decode available DVSEC details pciutils: Decode Compute eXpress Link DVSEC lib/header.h | 24 ++++ ls-ecaps.c | 73 +++++++++- tests/cap-dvsec | 340 ++++++++++++++++++++++++++++++++++++++++++++ tests/cap-dvsec-cxl | 340 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 776 insertions(+), 1 deletion(-) create mode 100644 tests/cap-dvsec create mode 100644 tests/cap-dvsec-cxl -- 2.26.0
