On Thu, Apr 09, 2020 at 04:25:40PM +0100, Luís Mendes wrote:
> Hi Bjorn,
>
> I've good news. I've found the culprit and it is a pretty simple
> issue, however the good solution is not obvious to me.
> Can you help in finding the best way to patch this issue?
>
> So first detailing the problem in file setup_bus.c there is this *if
> condition* to ignore resources from classless devices and so
> it is that this Google/Coral Edge TPU is a classless device with class 0xff:
>
> static void __dev_sort_resources(struct pci_dev *dev, struct list_head *head)
> {
> u16 class = dev->class >> 8;
>
> pci_info(dev, "%s\n", __func__);
> /* Don't touch classless devices or host bridges or IOAPICs */
> if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
> return;
> ....
>
> So the one possible trivial, non generic, attempt that works is to do:
> static void __dev_sort_resources(struct pci_dev *dev, struct list_head *head)
> {
> u16 class = dev->class >> 8;
>
> pci_info(dev, "%s\n", __func__);
> /* Don't touch classless devices or host bridges or IOAPICs */
> if ((class == PCI_CLASS_NOT_DEFINED && !(dev->vendor == 0x1ac1 &&
> dev->device==0x089a)) || class == PCI_CLASS_BRIDGE_HOST)
> return;
> ....
>
> What is your suggestion to make the solution generic? Create a
> whitelist? Remove this verification? I have no idea... nothing sounds
> good to me...
Good detective work, thanks for chasing this down!
I should have seen that check when adding the debug. Guess I thought
"sort", hmmm, that just re-orders things without actually changing the
content. But pdev_sort_resources() in fact *adds* resources to a
list, and if resources aren't on the list, we apparently don't assign
space for them.
In any event, I would first check to see if there's an Edge TPU
firmware update that might set the class code.
If not, we should probably add a quirk to override the class code,
similar to quirk_eisa_bridge(), fixup_rev1_53c810(),
fixup_ti816x_class(), quirk_tw686x_class().
Bjorn
