Compute eXpress Link[1] is a new CPU interconnected created with
workload accelerators in mind. The interconnect relies on PCIe Electrial
and Physical interconnect for communication.
Moreover, CXL bus hierarchy appear, to the OS, as an ACPI-described PCIe
Root Bridge with Integrated Endpoint.
I'm interested in feedback on how best to handle the case of DVSEC for CXL.
Up until this point it has been a catch-all:
case PCI_EXT_CAP_ID_DVSEC:
- printf("Designated Vendor-Specific <?>\n");
+ cap_cxl(d, where);
break;
Should I retain the general printf() in the case of the absence of CXL?
Or other suggestions?
Best regards,
Sean
[1] https://www.computeexpresslink.org
Sean V Kelley (1):
lspci: Add basic decode support for Compute eXpress Link
lib/header.h | 25 +++++++++++++++++++++++++
ls-ecaps.c | 29 ++++++++++++++++++++++++++++-
tests/cap-cxl-dvsec | 8 ++++++++
3 files changed, 61 insertions(+), 1 deletion(-)
create mode 100644 tests/cap-cxl-dvsec
--
2.26.0
