On Mon, Mar 23, 2020 at 5:24 PM Thomas Gleixner <tglx@xxxxxxxxxxxxx> wrote: > > Mathias Nyman <mathias.nyman@xxxxxxxxxxxxxxx> writes: > > On 23.3.2020 16.10, Thomas Gleixner wrote: > >> > >> thanks for providing the data. I think I decoded the issue. Can you > >> please test the patch below? > > > > Unfortunately it didn't help. > > I did not expect that to help, simply because the same issue is caught > by the loop in fixup_irqs(). What I wanted to make sure is that there is > not something in between which causes the latter to fail. > > So I stared at the trace data earlier today and looked at the xhci irq > events. They are following a more or less periodic schedule and the > forced migration on CPU hotplug hits definitely in the time frame where > the next interrupt should be raised by the device. > > 1) First off all I do not have to understand why new systems released > in 2020 still use non-maskable MSI which is the root cause of all of > this trouble especially in Intel systems which are known to have > this disastrouos interrupt migration troubles. > > Please tell your hardware people to stop this. > > 2) I have no idea why the two step mechanism fails exactly on this > system. I tried the same test case on a skylake client and I can > clearly see from the traces that the interrupt raised in the device > falls exactly into the two step update and causes the IRR to be set > which resolves the situation by IPI'ing the new target CPU. > > I have not found a single instance of IPI recovery in your > traces. Instead of that your system stops working in exactly this > situation. > > The two step mechanism tries to work around the fact that PCI does > not support a 64bit atomic config space update. So we carefully avoid > changing more than one 32bit value at a time, i.e. we change first > the vector and then the destination ID (part of address_lo). This > ensures that the message is consistent all the time. > > But obviously on your system this does not work as expected. Why? I > really can't tell. > > Please talk to your hardware folks. > > And of course all of this is so well documented that all of us can > clearly figure out what's going on... I won't pretend to know what's going on, so I'll preface this by labeling it all as "flailing", but: I wonder if there's some way the interrupt can get delayed between XHCI snapping the torn value and it finding its way into the IRR. For instance, if xhci read this value at the start of their interrupt moderation timer period, that would be awful (I hope they don't do this). One test patch would be to carve out 8 vectors reserved for xhci on all cpus. Whenever you change the affinity, the assigned vector is always reserved_base + cpu_number. That lets you exercise the affinity switching code, but in a controlled manner where torn interrupts could be easily seen (ie hey I got an interrupt on cpu 4's vector but I'm cpu 2). I might struggle to write such a change, but in theory it's doable. Actually the slightly easier experiment might be to reserve a single vector for xhci on all cores. We'd strongly expect the problem to go away, since now there's no more torn writes since the vector is always the same. If it somehow didn't go away, you'd know there's more to the story. I was alternately trying to build a theory in my head about the write somehow being posted and getting out of order, but I don't think that can happen. Another experiment would be to try my old patch in [1]. I'm not advocating for this patch as a solution, Thomas and Bjorn have convinced me that it will break the rest of the world. But your PCI device 0xa3af seems to be Comet Lake. I was also on Comet Lake. So I'd expect to at least see it mask your problem. Again, if it didn't, that might be an interesting datapoint. [1] https://lore.kernel.org/lkml/20200117162444.v2.1.I9c7e72144ef639cc135ea33ef332852a6b33730f@changeid/ -Evan
