On Sun, Mar 8, 2020 at 12:41 PM Matt Turner <mattst88@xxxxxxxxx> wrote: > > On Sun, Mar 8, 2020 at 8:30 AM Ivan Kokshaysky <ink@xxxxxxxxxxxxxxxxxxxx> wrote: > > Wholeheartedly agree. In fact, changes to generic PCI code required > > for proper root bus sizing are quite minimal now since we have > > struct pci_host_bridge. It's mostly additional checks for bus->self > > being NULL (as it normally is on the root bus) in the > > __pci_bus_size_bridges() path, plus new bridge->size_windows flag. > > See patch below (tested on UP1500). Note that on irongate we're > > only interested in calculation of non-prefetchable PCI memory aperture, > > but one can do the same for io and prefetchable memory as well. > > Thanks Ivan! The patch works for me as well. Bjorn, what would you like the next step to be? If the PCI bits are fine with you, I assume you'd like them to go through your tree, etc? I'm perfectly happy to see the alpha bits go through the same tree.
