From: Stanislav Spassov <stanspas@xxxxxxxxx> So far, pci_bridge_wait_for_secondary_bus() was only invoked by PM code after (runtime) resume of devices, but it naturally makes sense for handling post-SBR waiting as well. It uses the PCI_PM_D3COLD_WAIT value (100ms), potentially overridden on a per-device basis to a lower-value, as the basis for determining how long to wait, and handles special cases such as legacy PCI devices (requiring Trhfa), and the different starting points for the waiting time depending on PCIe port speed. On PCI Express, there will be cases where the new code sleeps far less than the 1s being replaced by this patch. This should be okay, because PCI Express Base Specification Revision 5.0 Version 1.0 (May 22, 2019) in Section 6.6.1 "Conventional Reset" only notes 100ms as the minimum waiting time. After this time, the OS is permitted to issue Configuration Requests, but it is possible that the device responds with Configuration Request Retry Status (CRS) Completions, rather than Successful Completion. Returning CRS can go on for up to 1 second after a Conventional Reset (such as SBR) before the OS can consider the device broken. This additional wait is handled by pci_dev_wait. Currently, the only callchain that lands in the function modified by this patch starts at pci_bridge_secondary_bus_reset which invokes one out of two versions of pcibios_reset_secondary_bus that both end with a call to pci_reset_secondary_bus. Afterwards, pci_bridge_secondary_bus_reset always invokes pci_dev_wait. Signed-off-by: Stanislav Spassov <stanspas@xxxxxxxxx> --- drivers/pci/pci.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index ac8504d75c32..c1a866f733e9 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4800,14 +4800,7 @@ void pci_reset_secondary_bus(struct pci_dev *dev) ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); - /* - * Trhfa for conventional PCI is 2^25 clock cycles. - * Assuming a minimum 33MHz clock this results in a 1s - * delay before we can consider subordinate devices to - * be re-initialized. PCIe has some ways to shorten this, - * but we don't make use of them yet. - */ - ssleep(1); + pci_bridge_wait_for_secondary_bus(dev); } void __weak pcibios_reset_secondary_bus(struct pci_dev *dev) -- 2.25.1 Amazon Development Center Germany GmbH Krausenstr. 38 10117 Berlin Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B Sitz: Berlin Ust-ID: DE 289 237 879
