On Wed, Feb 19, 2020 at 12:17 AM Ard Biesheuvel <ardb@xxxxxxxxxx> wrote: > > On Wed, 19 Feb 2020 at 09:11, Marc Zyngier <maz@xxxxxxxxxx> wrote: > > > > On Tue, 18 Feb 2020 11:09:10 -0800 > > Alan Mikhak <alan.mikhak@xxxxxxxxxx> wrote: > > > > > On Sat, Feb 15, 2020 at 2:36 AM Marc Zyngier <maz@xxxxxxxxxx> wrote: > > > > > > > > On Sat, 15 Feb 2020 09:35:56 +0000, > > > > Ard Biesheuvel <ardb@xxxxxxxxxx> wrote: > > > > > > > > > > (updated some email addresses in cc, including my own) > > > > > > > > > > On Sat, 15 Feb 2020 at 01:54, Alan Mikhak <alan.mikhak@xxxxxxxxxx> wrote: > > > > > > > > > > > > Hi.. > > > > > > > > > > > > What is the right approach for adding MSI support for the generic > > > > > > Linux PCI host driver? > > > > > > > > > > > > I came across this patch which seems to address a similar > > > > > > situation. It seems to have been dropped in v3 of the patchset > > > > > > with the explanation "drop MSI patch [for now], since it > > > > > > turns out we may not need it". > > > > > > > > > > > > [PATCH 2/3] pci: designware: add separate driver for the MSI part of the RC > > > > > > https://lore.kernel.org/linux-pci/20170821192907.8695-3-ard.biesheuvel@xxxxxxxxxx/ > > > > > > > > > > > > [PATCH v2 2/3] pci: designware: add separate driver for the MSI part of the RC > > > > > > https://lore.kernel.org/linux-pci/20170824184321.19432-3-ard.biesheuvel@xxxxxxxxxx/ > > > > > > > > > > > > [PATCH v3 0/2] pci: add support for firmware initialized designware RCs > > > > > > https://lore.kernel.org/linux-pci/20170828180437.2646-1-ard.biesheuvel@xxxxxxxxxx/ > > > > > > > > > > > > > > > > For the platform in question, it turned out that we could use the MSI > > > > > block of the core's GIC interrupt controller directly, which is a much > > > > > better solution. > > > > > > > > > > In general, turning MSIs into wired interrupts is not a great idea, > > > > > since the whole point of MSIs is that they are sufficiently similar to > > > > > other DMA transactions to ensure that the interrupt won't arrive > > > > > before the related memory transactions have completed. > > > > > > > > > > If your interrupt controller does not have this capability, then yes, > > > > > you are stuck with this little widget that decodes an inbound write to > > > > > a magic address and turns it into a wired interrupt. > > > > > > > > I can only second this. It is much better to have a generic block > > > > implementing MSI *in a non multiplexed way*, for multiple reasons: > > > > > > > > - the interrupt vs DMA race that Ard mentions above, > > > > > > > > - MSIs are very often used to describe the state of per-CPU queues. If > > > > you multiplex MSIs behind a single multiplexing interrupt, it is > > > > always the same CPU that gets interrupted, and you don't benefit > > > > from having multiple queues at all. > > > > > > > > Even if you have to implement the support as a bunch of wired > > > > interrupts, there is still a lot of value in keeping a 1:1 mapping > > > > between MSIs and wires. > > > > > > > > Thanks, > > > > > > > > M. > > > > > > > > -- > > > > Jazz is not dead, it just smells funny. > > > > > > Ard and Marc, Thanks for you comments. I will take a look at the code > > > related to MSI block of GIC interrupt controller for some reference. > > > > GICv2m or GICv3 MBI are probably your best bets. Don't get anywhere near > > the GICv3 ITS, there lies madness. ;-) > > > > True, but for the record, it is the GICv3 ITS that I used on the > platform in question, allowing me to ignore the pseudo-MSI widget > entirely. > > > > I am looking into supporting MSI in a non-multiplexed way when using > > > ECAM and the generic Linux PCI host driver when Linux is booted > > > from U-Boot. > > > > I don't really get the relationship between ECAM and MSIs. They should > > be fairly independent, unless that has to do with the allowing the MSI > > doorbell to be reached from the PCIe endpoint. > > > > The idea is that the PCIe RC is programmed by firmware, and exposed to > the OS as generic ECAM. If you have enough iATU registers and enough > free address space, that is perfectly feasible. > > The problem is that the generic ECAM binding does not have any > provisions for MSI doorbell widgets that turn inbound writes to a > magic address into a wired interrupt. My patch models this as a > separate device, which allows a generic ECAM DT node to refer to it as > its MSI parent. > > > > > Specifically, what is the right approach for sharing the physical > > > address of the MSI data block used in Linux with U-Boot? > > > > > > I imagine the Linux driver for MSI interrupt controller allocates > > > some DMA-able memory for use as the MSI data block. The > > > U-Boot PCIe driver would program an inbound ATU region to > > > map mem writes from endpoint devices to that MSI data block > > > before booting Linux. > > > > The "MSI block" is really a piece of HW, not memory. So whatever you > > have to program in the PCIe RC must allow an endpoint to reach that > > device with a 32bit write. > > > > Indeed. Either your interrupt controller or your PCIe RC needs to > implement the doorbell, but using the former is by far the preferred > option. Ard and Marc, Thank you so much for your insightful comments. The generic PCI host driver uses ECAM as the access method to read/write PCI configuration registers but has no support for MSI. I imagine I could use the MSI widget model from Art's patch to implement a separate Linux interrupt handler for MSI interrupts. I'm not sure but the MSI widget seems to multiplex MSI interrupts to one wired interrupt since its MSI doorbell is a u32 value. The widget also has code for programming the address of the doorbell into Designware PCIe IP registers. I imagine I would separate the lines of code that programs the PCIe IP MSI registers and move that non-generic PCIe code from Linux to U-Boot "firmware". The MSI interrupt handler would then become more of a generic PCI MSI interrupt handler. The "MSI block" I refer to is a page of memory that I see being allocated and mapped for dma access from endpoint devices in the Designware PCI host driver function dw_pcie_msi_init(). The physical address of this MSI data block is programmed into Designware PCIe IP MSI registers by Designware host driver. I believe this is the target memory where endpoint MSI write requests would be targeted to. I imagine an inbound ATU region maps the bus transaction to a physical address within this MSI data block to support non-multiplexed MSI interrupt handling. Whether the doorbell is a u32 value or a block of memory, the chicken or the egg dilemma I have is how to share the address of the MSI data block between Linux and U-Boot. Since all programming code for PCIe IP would reside in the U-Boot PCIe driver, U-Boot would need to know the address of the MSI data block before it boots Linux. However, if the MSI interrupt widget dynamically allocates the MSI data block, it would contain no code to program the address into the PCIe IP. I wonder if the MSI data block can be a reserved block of memory whose physical address is predetermined and shared via the "reg" entry for the MSI widget between Linux and U-Boot? Would that make sense? Regards, Alan
