EPC/DesignWare core endpoint subsystems assume that the core registers are available always for SW to initialize. But, that may not be the case always. For example, Tegra194 hardware has the core running on a clock that is derived from reference clock that is coming into the endpoint system from host. Hence core is made available asynchronously based on when host system is going for enumeration of devices. To accommodate this kind of hardwares, support is required to defer the core initialization until the respective platform driver informs the EPC/DWC endpoint sub-systems that the core is indeed available for initiaization. This patch series is attempting to add precisely that. This series is based on Kishon's patch that adds notification mechanism support from EPC to EPF @ http://patchwork.ozlabs.org/patch/1236793/ from the series @ http://patchwork.ozlabs.org/project/linux-pci/list/?series=158088 V3: * Rebased this series on top of kishon's new patch series as mentioned above * Added Acked-by: Kishon Vijay Abraham I <kishon@xxxxxx> V2: * Addressed review comments from Kishon Vidya Sagar (5): PCI: endpoint: Add core init notifying feature PCI: dwc: Refactor core initialization code for EP mode PCI: endpoint: Add notification for core init completion PCI: dwc: Add API to notify core initialization completion PCI: pci-epf-test: Add support to defer core initialization .../pci/controller/dwc/pcie-designware-ep.c | 79 +++++++----- drivers/pci/controller/dwc/pcie-designware.h | 11 ++ drivers/pci/endpoint/functions/pci-epf-test.c | 118 ++++++++++++------ drivers/pci/endpoint/pci-epc-core.c | 19 ++- include/linux/pci-epc.h | 2 + include/linux/pci-epf.h | 5 + 6 files changed, 164 insertions(+), 70 deletions(-) -- 2.17.1
