On Sun, 2020-02-09 at 16:37 +0100, Thomas Gleixner wrote: > Sean, > > Thomas Gleixner <tglx@xxxxxxxxxxxxx> writes: > > Sean V Kelley <sean.v.kelley@xxxxxxxxxxxxxxx> writes: > > > So I will ensure we actually create useful information pointing > > > to this > > > behavior either in kernel docs or online as in a white paper or > > > both. > > > > Great. > > > > > > As we have already quirks in drivers/pci/quirks.c which handle > > > > the > > > > same issue on older chipsets, we really should add one for > > > > these kind > > > > of systems to avoid fiddling with the BIOS (which you can, but > > > > most > > > > people cannot). > > > Agreed, and I will follow-up with Kar Hin Ong to get them added. > > > > Much appreciated. > > Any update on this? Hi Thomas, I've been working with Kar Hin in attempting to follow a similar pattern to the earlier PCI quirks done with ESB / ESB2 chipsets. However, the optional INTX routing table which was a part of the original quirk done about 10 years ago changed by the time these Haswell PCH arrived. The later PCH aligned with the BIOS switch becoming available and the deprecation of the bypass routing. We're testing a few more things, and I hope to have a conclusion this week. Thanks, Sean > > Thanks, > > tglx
