From: Bjorn Helgaas > Sent: 30 January 2020 19:01 .. > > > You could learn this either via a PCIe analyzer (expensive piece of > > > hardware) or possibly some logic in the FPGA that would log PCIe > > > transactions in a buffer and make them accessible via some other > > > interface (you mentioned it had parallel and other interfaces). You can probably use the Xilinx equivalent of Altera 'signaltap' to work out what is happening within the fpga. David - Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK Registration No: 1397386 (Wales)
