BARs and bridge windows are only allowed to be assigned to their
parent bus's bridge windows, going up to the root complex's resources.
So additional limitations on BAR address are not needed, and the
PCIBIOS_MIN_MEM can be ignored.
Besides, the value of PCIBIOS_MIN_MEM reported by the BIOS 1.3 on
Supermicro H11SSL-i via e820__setup_pci_gap():
[mem 0xebff1000-0xfe9fffff] available for PCI devices
is only suitable for a single RC out of four:
pci_bus 0000:00: root bus resource [mem 0xec000000-0xefffffff window]
pci_bus 0000:20: root bus resource [mem 0xeb800000-0xebefffff window]
pci_bus 0000:40: root bus resource [mem 0xeb200000-0xeb5fffff window]
pci_bus 0000:60: root bus resource [mem 0xe8b00000-0xeaffffff window]
, which makes the AMD EPYC 7251 unable to boot with this movable BARs
patchset.
Signed-off-by: Sergei Miroshnichenko <s.miroshnichenko@xxxxxxxxx>
---
drivers/pci/setup-res.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
index a7d81816d1ea..4043aab021dd 100644
--- a/drivers/pci/setup-res.c
+++ b/drivers/pci/setup-res.c
@@ -246,12 +246,13 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
int resno, resource_size_t size, resource_size_t align)
{
struct resource *res = dev->resource + resno;
- resource_size_t min;
+ resource_size_t min = 0;
int ret;
resource_size_t start = (resource_size_t)-1;
resource_size_t end = 0;
- min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
+ if (!pci_can_move_bars)
+ min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
if (pci_can_move_bars && dev->subordinate && resno >= PCI_BRIDGE_RESOURCES) {
struct pci_bus *child_bus = dev->subordinate;
--
2.24.1
