On Sat, Jan 11, 2020 at 12:45:00AM +0530, Vidya Sagar wrote: > The PCIe controller in Tegra194 SoC is not completely ECAM-compliant. > With the current hardware design limitations in place, ECAM can be enabled > only for one controller (C5 controller to be precise) with bus numbers > starting from 160 instead of 0. A different approach is taken to avoid this > abnormal way of enabling ECAM for just one controller but to enable > configuration space access for all the other controllers. In this approach, > ops are added through MCFG quirk mechanism which access the configuration > spaces by dynamically programming iATU (internal AddressTranslation Unit) > to generate respective configuration accesses just like the way it is > done in DesignWare core sub-system. > > Signed-off-by: Vidya Sagar <vidyas@xxxxxxxxxx> > Reported-by: kbuild test robot <lkp@xxxxxxxxx> > --- > V3: > * Removed MCFG address hardcoding in pci_mcfg.c file > * Started using 'dbi_base' for accessing root port's own config space > * and using 'config_base' for accessing config space of downstream hierarchy > > V2: > * Fixed build issues reported by kbuild test bot > > drivers/acpi/pci_mcfg.c | 7 ++ > drivers/pci/controller/dwc/Kconfig | 3 +- > drivers/pci/controller/dwc/Makefile | 2 +- > drivers/pci/controller/dwc/pcie-tegra194.c | 102 +++++++++++++++++++++ > include/linux/pci-ecam.h | 1 + > 5 files changed, 113 insertions(+), 2 deletions(-) Acked-by: Thierry Reding <treding@xxxxxxxxxx>
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