This IP could supports USB3.0 and PCIe. Signed-off-by: Shawn Lin <shawn.lin@xxxxxxxxxxxxxx> --- .../bindings/phy/rockchip,inno-combophy.yaml | 84 ++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/rockchip,inno-combophy.yaml diff --git a/Documentation/devicetree/bindings/phy/rockchip,inno-combophy.yaml b/Documentation/devicetree/bindings/phy/rockchip,inno-combophy.yaml new file mode 100644 index 0000000..d647ab3 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip,inno-combophy.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,inno-combophy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip USB3.0/PCI-e combo phy + +maintainers: + - Shawn Lin <shawn.lin@xxxxxxxxxxxxxx> + - William Wu <william.wu@xxxxxxxxxxxxxx> + +properties: + "#phy-cells": + const: 1 + + compatible: + enum: + - rockchip,rk1808-combphy + + reg: + maxItems: 1 + + clocks: + items: + - description: PLL reference clock + + clock-names: + items: + - const: refclk + + resets: + items: + - description: OTG unit reset line + - description: POR unit reset line + - description: APB interface reset line + - description: PIPE unit reset line + + reset-names: + items: + - const: otg-rst + - const: combphy-por + - const: combphy-apb + - const: combphy-pipe + + rockchip,combphygrf: + items: + - description: The grf for COMBPHY configuration and state registers. + +required: + - "#phy-cells" + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - rockchip,combphygrf + +additionalProperties: false + +examples: + - | + combphy_grf: syscon@fe018000 { + compatible = "rockchip,usb3phy-grf", "syscon"; + reg = <0x0 0xfe018000 0x0 0x8000>; + }; + + combphy: phy@ff380000 { + compatible = "rockchip,rk1808-combphy"; + reg = <0x0 0xff380000 0x0 0x10000>; + #phy-cells = <1>; + clocks = <&cru SCLK_PCIEPHY_REF>; + clock-names = "refclk"; + assigned-clocks = <&cru SCLK_PCIEPHY_REF>; + assigned-clock-rates = <25000000>; + resets = <&cru SRST_USB3_OTG_A>, <&cru SRST_PCIEPHY_POR>, + <&cru SRST_PCIEPHY_P>, <&cru SRST_PCIEPHY_PIPE>; + reset-names = "otg-rst", "combphy-por", + "combphy-apb", "combphy-pipe"; + rockchip,combphygrf = <&combphy_grf>; + }; + +... -- 1.9.1
