> -----Original Message----- > From: Kishon Vijay Abraham I <kishon@xxxxxx> > Sent: 2020年1月9日 18:19 > To: Bjorn Helgaas <helgaas@xxxxxxxxxx>; Gustavo Pimentel > <gustavo.pimentel@xxxxxxxxxxxx>; Xiaowei Bao <xiaowei.bao@xxxxxxx> > Cc: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>; Andrew Murray > <andrew.murray@xxxxxxx>; Murali Karicheri <m-karicheri2@xxxxxx>; Jingoo > Han <jingoohan1@xxxxxxxxx>; linux-pci@xxxxxxxxxxxxxxx; > linux-kernel@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx > Subject: Re: [PATCH 0/4] Redesign MSI-X support in PCIe Endpoint Core > > Hi, > > On 12/12/19 4:16 AM, Bjorn Helgaas wrote: > > On Wed, Dec 11, 2019 at 06:16:04PM +0530, Kishon Vijay Abraham I wrote: > >> Existing MSI-X support in Endpoint core has limitations: > >> 1) MSIX table (which is mapped to a BAR) is not allocated by > >> anyone. Ideally this should be allocated by endpoint > >> function driver. > >> 2) Endpoint controller can choose any random BARs for MSIX > >> table (irrespective of whether the endpoint function driver > >> has allocated memory for it or not) > >> > >> In order to avoid these limitations, pci_epc_set_msix() is modified > >> to include BAR Indicator register (BIR) configuration and MSIX table > >> offset as arguments. This series also fixed MSIX support in dwc > >> driver and add MSI-X support in Cadence PCIe driver. > >> > >> The previous version of Cadence EP MSI-X support is @ [1]. > >> This series is created on top of [2] > >> > >> [1] -> > >> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat > >> > chwork.ozlabs.org%2Fpatch%2F971160%2F&data=02%7C01%7Cxiaowei > .bao% > >> > 40nxp.com%7Ca1c78017032c4f4882b708d794ed1e9c%7C686ea1d3bc2b4c6 > fa92cd9 > >> > 9c5c301635%7C0%7C0%7C637141618459605704&sdata=o1gFrMe%2B > DERcNIVjK > >> 5ZRJnDmO1QfAKQostQci05%2BrJA%3D&reserved=0 > >> [2] -> > >> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flore > >> .kernel.org%2Fr%2F20191209092147.22901-1-kishon%40ti.com&dat > a=02% > >> > 7C01%7Cxiaowei.bao%40nxp.com%7Ca1c78017032c4f4882b708d794ed1e9 > c%7C686 > >> > ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637141618459605704&a > mp;sdata= > >> > fdZEFSCBc89vBEZlCUpuoIjZqrsqWPdNaNt3nMFdO0I%3D&reserved=0 > >> > >> Alan Douglas (1): > >> PCI: cadence: Add MSI-X support to Endpoint driver > >> > >> Kishon Vijay Abraham I (3): > >> PCI: endpoint: Fix ->set_msix() to take BIR and offset as arguments > >> PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSIX table > >> address > >> PCI: keystone: Add AM654 PCIe Endpoint to raise MSIX interrupt > > > > Trivial nits: > > > > - There's a mix of "MSI-X" and "MSIX" in the subjects, commit logs, > > and comments. I prefer "MSI-X" to match usage in the spec. > > > > - "Fixes:" tags need not include "commit". It doesn't *hurt* > > anything, but it takes up space that could be used for the > > subject. > > > > - Commit references typically use a 12-char SHA1. Again, doesn't > > hurt anything. > > I'll fix all this in my next revision. > > Xiaowei, Gustavo, > > The issues we discussed in [1] should be fixed with this series. Can you help > test this in your platforms? OK, I will test it when I am free, and give the feedback to you. Thanks Xiaowei > > [1] -> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flkml.or > g%2Flkml%2F2019%2F11%2F6%2F678&data=02%7C01%7Cxiaowei.bao > %40nxp.com%7Ca1c78017032c4f4882b708d794ed1e9c%7C686ea1d3bc2b4c > 6fa92cd99c5c301635%7C0%7C0%7C637141618459605704&sdata=nmJ > GiBLcEUnBFTaaoJUOhL290cmA7F%2F2uBnTpvw9ugo%3D&reserved=0 > > Thanks > Kishon > >
