Hi,
I have module with Xilinx FPGA. It implements UART(s), SPI(s),
parallel I/O and interfaces them to the Host CPU via PCI Express bus.
I see that my system freezes without capturing the crash dump for
certain tests. I debugged this issue and it was tracked down to the
below mentioned interrupt handler code.
In ISR, first reads the Interrupt Status register using ‘readl()’ as
given below.
status = readl(ctrl->reg + INT_STATUS);
And then clears the pending interrupts using ‘writel()’ as given blow.
writel(status, ctrl->reg + INT_STATUS);
I've noticed a kernel hang if INT_STATUS register read again after
clearing the pending interrupts.
Can someone clarify me why the kernel hangs without crash dump incase
if I read the INT_STATUS register using readl() after clearing the
pending bits?
Can readl() block?
Snippet of the ISR code is given blow:
https://pastebin.com/WdnZJZF5
static irqreturn_t pcie_isr(int irq, void *dev_id)
{
struct test_device *ctrl = data;
u32 status;
…
status = readl(ctrl->reg + INT_STATUS);
/*
* Check to see if it was our interrupt
*/
if (!(status & 0x000C))
return IRQ_NONE;
/* Clear the interrupt */
writel(status, ctrl->reg + INT_STATUS);
if (status & 0x0004) {
/*
* Tx interrupt pending.
*/
....
}
if (status & 0x0008) {
/* Rx interrupt Pending */
/* The system freezes if I read again the INT_STATUS
register as given below */
status = readl(ctrl->reg + INT_STATUS);
....
}
..
return IRQ_HANDLED;
}
--
Thanks,
Sekhar
