On Fri, Dec 13, 2019 at 06:43:20PM +0530, Anvesh Salveru wrote:
> Many platforms use DesignWare controller but the PHY can be different in
> different platforms. If the PHY is compliant is to ZRX-DC specification
> it helps in low power consumption during power states.
>
> If current data rate is 8.0 GT/s or higher and PHY is not compliant to
> ZRX-DC specification, then after every 100ms link should transition to
> recovery state during the low power states.
>
> DesignWare controller provides GEN3_ZRXDC_NONCOMPL field in
> GEN3_RELATED_OFF to specify about ZRX-DC compliant PHY.
>
> Platforms with ZRX-DC compliant PHY can set phy_zrxdc_compliant variable
> to specify this property to the controller.
>
> Signed-off-by: Anvesh Salveru <anvesh.s@xxxxxxxxxxx>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@xxxxxxxxxxx>
> ---
> Changes w.r.t v5:
> - None
>
> drivers/pci/controller/dwc/pcie-designware.c | 6 ++++++
> drivers/pci/controller/dwc/pcie-designware.h | 4 ++++
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 820488d..36a01b7 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -556,4 +556,10 @@ void dw_pcie_setup(struct dw_pcie *pci)
> PCIE_PL_CHK_REG_CHK_REG_START;
> dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
> }
> +
> + if (pci->phy_zrxdc_compliant) {
This series doesn't update any DWC drivers to actually test and set the
phy_zrxdc_compliant flag. There isn't good justification for merging this
unless it has a user.
Thanks,
Andrew Murray
> + val = dw_pcie_readl_dbi(pci, PCIE_PORT_GEN3_RELATED);
> + val &= ~PORT_LOGIC_GEN3_ZRXDC_NONCOMPL;
> + dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val);
> + }
> }
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 5accdd6..36f7579 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -60,6 +60,9 @@
> #define PCIE_MSI_INTR0_MASK 0x82C
> #define PCIE_MSI_INTR0_STATUS 0x830
>
> +#define PCIE_PORT_GEN3_RELATED 0x890
> +#define PORT_LOGIC_GEN3_ZRXDC_NONCOMPL BIT(0)
> +
> #define PCIE_ATU_VIEWPORT 0x900
> #define PCIE_ATU_REGION_INBOUND BIT(31)
> #define PCIE_ATU_REGION_OUTBOUND 0
> @@ -249,6 +252,7 @@ struct dw_pcie {
> void __iomem *atu_base;
> u32 num_viewport;
> u8 iatu_unroll_enabled;
> + bool phy_zrxdc_compliant;
> struct pcie_port pp;
> struct dw_pcie_ep ep;
> const struct dw_pcie_ops *ops;
> --
> 2.7.4
>
