> -----Original Message-----
> From: Gustavo Pimentel <Gustavo.Pimentel@xxxxxxxxxxxx>
> Sent: Thursday, November 21, 2019 7:25 PM
> To: Anvesh Salveru <anvesh.s@xxxxxxxxxxx>; linux-kernel@xxxxxxxxxxxxxxx;
> linux-pci@xxxxxxxxxxxxxxx
> Cc: jingoohan1@xxxxxxxxx; pankaj.dubey@xxxxxxxxxxx;
> lorenzo.pieralisi@xxxxxxx; andrew.murray@xxxxxxx; bhelgaas@xxxxxxxxxx;
> kishon@xxxxxx; robh+dt@xxxxxxxxxx; mark.rutland@xxxxxxx
> Subject: RE: [PATCH v4 2/2] PCI: dwc: add support to handle ZRX-DC Compliant
> PHYs
>
> On Thu, Nov 21, 2019 at 3:20:8, Anvesh Salveru <anvesh.s@xxxxxxxxxxx>
> wrote:
>
> > Many platforms use DesignWare controller but the PHY can be different
> > in different platforms. If the PHY is compliant is to ZRX-DC
> > specification it helps in low power consumption during power states.
> >
> > If current data rate is 8.0 GT/s or higher and PHY is not compliant to
> > ZRX-DC specification, then after every 100ms link should transition to
> > recovery state during the low power states.
> >
> > DesignWare controller provides GEN3_ZRXDC_NONCOMPL field in
> > GEN3_RELATED_OFF to specify about ZRX-DC compliant PHY.
> >
> > Platforms with ZRX-DC compliant PHY can set phy_zrxdc_compliant
> > variable to specify this property to the controller.
> >
> > Signed-off-by: Anvesh Salveru <anvesh.s@xxxxxxxxxxx>
> > Signed-off-by: Pankaj Dubey <pankaj.dubey@xxxxxxxxxxx>
> > ---
> > drivers/pci/controller/dwc/pcie-designware.c | 6 ++++++
> > drivers/pci/controller/dwc/pcie-designware.h | 4 ++++
> > 2 files changed, 10 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.c
> > b/drivers/pci/controller/dwc/pcie-designware.c
> > index 820488d..36a01b7 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > @@ -556,4 +556,10 @@ void dw_pcie_setup(struct dw_pcie *pci)
> > PCIE_PL_CHK_REG_CHK_REG_START;
> > dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS,
> val);
> > }
> > +
> > + if (pci->phy_zrxdc_compliant) {
> > + val = dw_pcie_readl_dbi(pci, PCIE_PORT_GEN3_RELATED);
> > + val &= ~PORT_LOGIC_GEN3_ZRXDC_NONCOMPL;
> > + dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val);
> > + }
> > }
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h
> > b/drivers/pci/controller/dwc/pcie-designware.h
> > index 5a18e94..f43f986 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -60,6 +60,9 @@
> > #define PCIE_MSI_INTR0_MASK 0x82C
> > #define PCIE_MSI_INTR0_STATUS 0x830
> >
> > +#define PCIE_PORT_GEN3_RELATED 0x890
> > +#define PORT_LOGIC_GEN3_ZRXDC_NONCOMPL BIT(0)
> > +
> > #define PCIE_ATU_VIEWPORT 0x900
> > #define PCIE_ATU_REGION_INBOUND BIT(31)
> > #define PCIE_ATU_REGION_OUTBOUND 0
> > @@ -249,6 +252,7 @@ struct dw_pcie {
> > void __iomem *atu_base;
> > u32 num_viewport;
> > u8 iatu_unroll_enabled;
> > + bool phy_zrxdc_compliant;
>
> Typically is used u8 instead of bool, due to platform compatibility.
> I'd guess that checkpatch script should have reported this. Did you use it?
Checkpatch didn't report any error/warning.
We used bool here as phy_zrxdc_compliant will store the value returned by of_property_read_bool API.
I can see many places in drivers/pci/ where this API is used the value is stored in bool itself.
>
> > struct pcie_port pp;
> > struct dw_pcie_ep ep;
> > const struct dw_pcie_ops *ops;
> > --
> > 2.7.4
>
