On Thu, Nov 07, 2019 at 01:58:14PM +0900, Kunihiko Hayashi wrote:
> In order to avoid effect of the initial mode depending on SoCs,
> this patch sets the mode register to host(RC) mode.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@xxxxxxxxxxxxx>
> ---
> drivers/pci/controller/dwc/pcie-uniphier.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
Applied to pci/uniphier, thanks.
Lorenzo
> diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c
> index 3f30ee4..8fd7bad 100644
> --- a/drivers/pci/controller/dwc/pcie-uniphier.c
> +++ b/drivers/pci/controller/dwc/pcie-uniphier.c
> @@ -33,6 +33,10 @@
> #define PCL_PIPEMON 0x0044
> #define PCL_PCLK_ALIVE BIT(15)
>
> +#define PCL_MODE 0x8000
> +#define PCL_MODE_REGEN BIT(8)
> +#define PCL_MODE_REGVAL BIT(0)
> +
> #define PCL_APP_READY_CTRL 0x8008
> #define PCL_APP_LTSSM_ENABLE BIT(0)
>
> @@ -85,6 +89,12 @@ static void uniphier_pcie_init_rc(struct uniphier_pcie_priv *priv)
> {
> u32 val;
>
> + /* set RC MODE */
> + val = readl(priv->base + PCL_MODE);
> + val |= PCL_MODE_REGEN;
> + val &= ~PCL_MODE_REGVAL;
> + writel(val, priv->base + PCL_MODE);
> +
> /* use auxiliary power detection */
> val = readl(priv->base + PCL_APP_PM0);
> val |= PCL_SYS_AUX_PWR_DET;
> --
> 2.7.4
>
