On 11/11/19 7:29 AM, Nicolas Saenz Julienne wrote:
> Hi Jeremy,
> thanks for the review.
>
> On Mon, 2019-11-11 at 01:10 -0600, Jeremy Linton wrote:
[snip]
>>> +static const int pcie_offset_bcm2711[] = {
>>> + [RGR1_SW_INIT_1] = 0x9210,
>>> + [EXT_CFG_INDEX] = 0x9000,
>>> + [EXT_CFG_DATA] = 0x8000,
>>> +};
>>
>> Given that there is currently only a single set of register offsets,
>> this seems like it could be simpler.
>
> You're right, there is no need for it as of this series. But since we know
> we'll be supporting other SoCs in the near future I figured it was harmless to
> leave this as a dt dependent config.
I would rather leave it as is right now because while possibly
inefficient, adding a later series whose purpose is to add register
indirection would just clutter the review process IMHO, the way it is
right now does not hurt.
(please trim your replies to remove what you are not responding to).
--
Florian
