On Mon, Oct 21, 2019 at 05:55:55PM +0530, Anvesh Salveru wrote: > Add support for ZRX-DC compliant PHYs. If PHY is not compliant to ZRX-DC > specification, then after every 100ms link should transition to recovery > state during the low power states which increases power consumption. > > Platforms with ZRX-DC compliant PHY can use "snps,phy-zrxdc-compliant" > property in DesignWare controller DT node. > > Signed-off-by: Anvesh Salveru <anvesh.s@xxxxxxxxxxx> > Signed-off-by: Pankaj Dubey <pankaj.dubey@xxxxxxxxxxx> > --- > Documentation/devicetree/bindings/pci/designware-pcie.txt | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt > index 78494c4050f7..9507ac38ac89 100644 > --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt > @@ -38,6 +38,8 @@ Optional properties: > for data corruption. CDM registers include standard PCIe configuration > space registers, Port Logic registers, DMA and iATU (internal Address > Translation Unit) registers. > +- snps,phy-zrxdc-compliant: This property is needed if phy complies with the Strictly speaking, this is a property of the phy - not the controller that uses it. If I understand correctly, there are some DW based PCI controllers that use a phandle reference in DT to a Phy (such as fsl,imx6q-pcie.txt). Therefore it feels like this is in the wrong place. Is there a reason this isn't described in the Phy? Thanks, Andrew Murray > + ZRX-DC specification. > RC mode: > - num-viewport: number of view ports configured in hardware. If a platform > does not specify it, the driver assumes 2. > -- > 2.17.1 >
