> -----Original Message----- > From: Christoph Hellwig <hch@xxxxxxxxxxxxx> > Sent: Tuesday, October 15, 2019 1:46 PM > To: Pankaj Dubey <pankaj.dubey@xxxxxxxxxxx> > Cc: linux-pci@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; > bhelgaas@xxxxxxxxxx; andrew.murray@xxxxxxx; lorenzo.pieralisi@xxxxxxx; > gustavo.pimentel@xxxxxxxxxxxx; jingoohan1@xxxxxxxxx; vidyas@xxxxxxxxxx; > Anvesh Salveru <anvesh.s@xxxxxxxxxxx> > Subject: Re: [PATCH v3] PCI: dwc: Add support to add GEN3 related equalization > quirks > > On Tue, Oct 15, 2019 at 08:29:22AM +0530, Pankaj Dubey wrote: > > From: Anvesh Salveru <anvesh.s@xxxxxxxxxxx> > > > > In some platforms, PCIe PHY may have issues which will prevent linkup > > to happen in GEN3 or higher speed. In case equalization fails, link > > will fallback to GEN1. > > > > DesignWare controller gives flexibility to disable GEN3 equalization > > completely or only phase 2 and 3 of equalization. > > > > This patch enables the DesignWare driver to disable the PCIe GEN3 > > equalization by enabling one of the following quirks: > > - DWC_EQUALIZATION_DISABLE: To disable GEN3 equalization all phases > > - DWC_EQ_PHASE_2_3_DISABLE: To disable GEN3 equalization phase 2 & 3 > > > > Platform drivers can set these quirks via "quirk" variable of "dw_pcie" > > struct. > > Please submit this together with the changes to the dwc frontend driver that > actually wants to set these quirks. Is this something mandatory? As we discussed during first patch-set here [1] with Andrew, we have need of this patch (along with some other stuffs, which will be sent soon), to clean up our internal driver and make it ready for upstream. As of today we have some internal restrictions where we can't make it to upstream along with this patch. [1]: https://patchwork.ozlabs.org/patch/1160310/#2258262
