On Tue, Aug 06, 2019 at 08:49:46PM +0200, Remi Pommarel wrote: > On Wed, May 22, 2019 at 11:33:50PM +0200, Remi Pommarel wrote: > > When configuring pcie reset pin from gpio (e.g. initially set by > > u-boot) to pcie function this pin goes low for a brief moment > > asserting the PERST# signal. Thus connected device enters fundamental > > reset process and link configuration can only begin after a minimal > > 100ms delay (see [1]). > > > > Because the pin configuration comes from the "default" pinctrl it is > > implicitly configured before the probe callback is called: > > > > driver_probe_device() > > really_probe() > > ... > > pinctrl_bind_pins() /* Here pin goes from gpio to PCIE reset > > function and PERST# is asserted */ > > ... > > drv->probe() > > > > [1] "PCI Express Base Specification", REV. 4.0 > > PCI Express, February 19 2014, 6.6.1 Conventional Reset > > > > Signed-off-by: Remi Pommarel <repk@xxxxxxxxxxxx> > > --- > > Changes since v1: > > - Add a comment about pinctrl implicit pin configuration > > - Use more legible msleep > > - Use PCI_PM_D3COLD_WAIT macro > > > > Please note that I will unlikely be able to answer any comments from May > > 24th to June 10th. > > --- > > drivers/pci/controller/pci-aardvark.c | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c > > index 134e0306ff00..d998c2b9cd04 100644 > > --- a/drivers/pci/controller/pci-aardvark.c > > +++ b/drivers/pci/controller/pci-aardvark.c > > @@ -324,6 +324,14 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) > > reg |= PIO_CTRL_ADDR_WIN_DISABLE; > > advk_writel(pcie, reg, PIO_CTRL); > > > > + /* > > + * PERST# signal could have been asserted by pinctrl subsystem before > > + * probe() callback has been called, making the endpoint going into > > + * fundamental reset. As required by PCI Express spec a delay for at > > + * least 100ms after such a reset before link training is needed. > > + */ > > + msleep(PCI_PM_D3COLD_WAIT); > > + > > /* Start link training */ > > reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); > > reg |= PCIE_CORE_LINK_TRAINING; > > -- > > 2.20.1 > > Gentle ping. Thomas, sorry for the delay, unless you object I would merge this patch, I need your ACK to proceed though. Thanks, Lorenzo
