On Mon, Sep 16, 2019 at 13:24:1, Andrew Murray <andrew.murray@xxxxxxx> wrote: > On Mon, Sep 16, 2019 at 04:36:33PM +0530, Pankaj Dubey wrote: > > > > > > > -----Original Message----- > > > From: Andrew Murray <andrew.murray@xxxxxxx> > > > Sent: Monday, September 16, 2019 3:46 PM > > > To: Pankaj Dubey <pankaj.dubey@xxxxxxxxxxx> > > > Cc: linux-pci@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; > > > jingoohan1@xxxxxxxxx; gustavo.pimentel@xxxxxxxxxxxx; > > > lorenzo.pieralisi@xxxxxxx; bhelgaas@xxxxxxxxxx; Anvesh Salveru > > > <anvesh.s@xxxxxxxxxxx> > > > Subject: Re: [PATCH v2] PCI: dwc: Add support to add GEN3 related > > equalization > > > quirks > > > > > > On Fri, Sep 13, 2019 at 04:09:50PM +0530, Pankaj Dubey wrote: > > > > From: Anvesh Salveru <anvesh.s@xxxxxxxxxxx> > > > > > > > > In some platforms, PCIe PHY may have issues which will prevent linkup > > > > to happen in GEN3 or higher speed. In case equalization fails, link > > > > will fallback to GEN1. > > > > > > > > DesignWare controller gives flexibility to disable GEN3 equalization > > > > completely or only phase 2 and 3 of equalization. > > > > > > > > This patch enables the DesignWare driver to disable the PCIe GEN3 > > > > equalization by enabling one of the following quirks: > > > > - DWC_EQUALIZATION_DISABLE: To disable GEN3 equalization all phases > > > > - DWC_EQ_PHASE_2_3_DISABLE: To disable GEN3 equalization phase 2 & 3 > > > > > > > > Platform drivers can set these quirks via "quirk" variable of "dw_pcie" > > > > struct. > > > > > > > > Signed-off-by: Anvesh Salveru <anvesh.s@xxxxxxxxxxx> > > > > Signed-off-by: Pankaj Dubey <pankaj.dubey@xxxxxxxxxxx> > > > > --- > > > > Patchset v1 can be found at: > > > > - 1/2: https://urldefense.proofpoint.com/v2/url?u=https-3A__lkml.org_lkml_2019_9_10_443&d=DwIBAg&c=DPL6_X_6JkXFx7AXWqB0tg&r=bkWxpLoW-f-E3EdiDCCa0_h0PicsViasSlvIpzZvPxs&m=MtEKKeJsQvi2UM1eSZUv2vPLLxrYU0aI1Ry4ICIDaiQ&s=s_nPmMNbQFswYRxQgBkeg4H9J_0FEtzRE-0AruC5WI4&e= > > > > - 2/2: https://urldefense.proofpoint.com/v2/url?u=https-3A__lkml.org_lkml_2019_9_10_444&d=DwIBAg&c=DPL6_X_6JkXFx7AXWqB0tg&r=bkWxpLoW-f-E3EdiDCCa0_h0PicsViasSlvIpzZvPxs&m=MtEKKeJsQvi2UM1eSZUv2vPLLxrYU0aI1Ry4ICIDaiQ&s=kkfdwcX6bYcLrnJSgw_GcMMGAjnDTMtN2v6svWuANpk&e= > > > > > > > > Changes w.r.t v1: > > > > - Squashed two patches from v1 into one as suggested by Gustavo > > > > - Addressed review comments from Andrew > > > > > > > > drivers/pci/controller/dwc/pcie-designware.c | 12 ++++++++++++ > > > > drivers/pci/controller/dwc/pcie-designware.h | 9 +++++++++ > > > > 2 files changed, 21 insertions(+) > > > > > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c > > > > b/drivers/pci/controller/dwc/pcie-designware.c > > > > index 7d25102..97fb18d 100644 > > > > --- a/drivers/pci/controller/dwc/pcie-designware.c > > > > +++ b/drivers/pci/controller/dwc/pcie-designware.c > > > > @@ -466,4 +466,16 @@ void dw_pcie_setup(struct dw_pcie *pci) > > > > break; > > > > } > > > > dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); > > > > + > > > > + if (pci->quirk & DWC_EQUALIZATION_DISABLE) { > > > > + val = dw_pcie_readl_dbi(pci, PCIE_PORT_GEN3_RELATED); > > > > + val |= PORT_LOGIC_GEN3_EQ_DISABLE; > > > > + dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val); > > > > + } > > > > + > > > > + if (pci->quirk & DWC_EQ_PHASE_2_3_DISABLE) { > > > > + val = dw_pcie_readl_dbi(pci, PCIE_PORT_GEN3_RELATED); > > > > + val |= PORT_LOGIC_GEN3_EQ_PHASE_2_3_DISABLE; > > > > + dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val); > > > > + } > > > > } > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h > > > > b/drivers/pci/controller/dwc/pcie-designware.h > > > > index ffed084..e428b62 100644 > > > > --- a/drivers/pci/controller/dwc/pcie-designware.h > > > > +++ b/drivers/pci/controller/dwc/pcie-designware.h > > > > @@ -29,6 +29,10 @@ > > > > #define LINK_WAIT_MAX_IATU_RETRIES 5 > > > > #define LINK_WAIT_IATU 9 > > > > > > > > +/* Parameters for GEN3 related quirks */ > > > > +#define DWC_EQUALIZATION_DISABLE BIT(1) > > > > +#define DWC_EQ_PHASE_2_3_DISABLE BIT(2) > > > > + > > > > /* Synopsys-specific PCIe configuration registers */ > > > > #define PCIE_PORT_LINK_CONTROL 0x710 > > > > #define PORT_LINK_MODE_MASK GENMASK(21, 16) > > > > @@ -60,6 +64,10 @@ > > > > #define PCIE_MSI_INTR0_MASK 0x82C > > > > #define PCIE_MSI_INTR0_STATUS 0x830 > > > > > > > > +#define PCIE_PORT_GEN3_RELATED 0x890 > > > > > > I hadn't noticed this in the previous version - what is the proper name > > for this > > > register? Does it end in _RELATED? > > > > As per SNPS databook the name of the register is "GEN3_RELATED_OFF". It is > > port logic register so, to keep similarity with other port logic registers > > in this file we named it as "PCIE_PORT_GEN3_RELATED". > > OK. > > Reviewed-by: Andrew Murray <andrew.murray@xxxxxxx> > > Also is the SNPS databook publicly available? I'd be interested in reading > it. The databook isn't openly available, sorry. Gustavo > > Thanks, > > Andrew Murray > > > > > > > > > Thanks, > > > > > > Andrew Murray > > > > > > > +#define PORT_LOGIC_GEN3_EQ_PHASE_2_3_DISABLE BIT(9) > > > > +#define PORT_LOGIC_GEN3_EQ_DISABLE BIT(16) > > > > + > > > > #define PCIE_ATU_VIEWPORT 0x900 > > > > #define PCIE_ATU_REGION_INBOUND BIT(31) > > > > #define PCIE_ATU_REGION_OUTBOUND 0 > > > > @@ -244,6 +252,7 @@ struct dw_pcie { > > > > struct dw_pcie_ep ep; > > > > const struct dw_pcie_ops *ops; > > > > unsigned int version; > > > > + unsigned int quirk; > > > > }; > > > > > > > > #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, > > > > pp) > > > > -- > > > > 2.7.4 > > > > > >
