From: Anvesh Salveru <anvesh.s@xxxxxxxxxxx> In some platforms, PCIe PHY may have issues which will prevent linkup to happen in GEN3 or high speed. In case equalization fails, link will fallback to GEN1. Designware controller gives flexibility to disable GEN3 equalization completely or only phase 2 and 3. Platform drivers can disable equalization phase 2 and 3, by setting dwc_pci_quirk flag DWC_EQUALIZATION_DISABLE. Signed-off-by: Anvesh Salveru <anvesh.s@xxxxxxxxxxx> Signed-off-by: Pankaj Dubey <pankaj.dubey@xxxxxxxxxxx> --- drivers/pci/controller/dwc/pcie-designware.c | 3 +++ drivers/pci/controller/dwc/pcie-designware.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index bf82091..97a8268 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -472,5 +472,8 @@ void dw_pcie_setup(struct dw_pcie *pci) if (pci->dwc_pci_quirk & DWC_EQUALIZATION_DISABLE) val |= PORT_LOGIC_GEN3_EQ_DISABLE; + if (pci->dwc_pci_quirk & DWC_EQ_PHASE_2_3_DISABLE) + val |= PORT_LOGIC_GEN3_EQ_PHASE_2_3_DISABLE; + dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index a1453c5..b541508 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -31,6 +31,7 @@ /* Parameters for PCIe Quirks */ #define DWC_EQUALIZATION_DISABLE 0x1 +#define DWC_EQ_PHASE_2_3_DISABLE 0x2 /* Synopsys-specific PCIe configuration registers */ #define PCIE_PORT_LINK_CONTROL 0x710 @@ -65,6 +66,7 @@ #define PCIE_PORT_GEN3_RELATED 0x890 #define PORT_LOGIC_GEN3_EQ_DISABLE BIT(16) +#define PORT_LOGIC_GEN3_EQ_PHASE_2_3_DISABLE BIT(9) #define PCIE_ATU_VIEWPORT 0x900 #define PCIE_ATU_REGION_INBOUND BIT(31) -- 2.7.4
