Hi Dilip, On 9/4/2019 6:10 PM, Dilip Kota wrote:
The Intel PCIe RC controller is Synopsys Designware based PCIe core. Add YAML schemas for PCIe in RC mode present in Intel Universal Gateway soc. Signed-off-by: Dilip Kota <eswara.kota@xxxxxxxxxxxxxxx> --- changes on v3: Add the appropriate License-Identifier Rename intel,rst-interval to 'reset-assert-us'
rst->interval to reset-assert-ms(should be typo error)
Add additionalProperties: false Rename phy-names to 'pciephy' Remove the dtsi node split of SoC and board in the example Add #interrupt-cells = <1>; or else interrupt parsing will fail Name yaml file with compatible name .../devicetree/bindings/pci/intel,lgm-pcie.yaml | 137 +++++++++++++++++++++ 1 file changed, 137 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/intel,lgm-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/intel,lgm-pcie.yaml b/Documentation/devicetree/bindings/pci/intel,lgm-pcie.yaml new file mode 100644 index 000000000000..5e5cc7fd66cd --- /dev/null +++ b/Documentation/devicetree/bindings/pci/intel,lgm-pcie.yaml @@ -0,0 +1,137 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/intel-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel AXI bus based PCI express root complex + +maintainers: + - Dilip Kota <eswara.kota@xxxxxxxxxxxxxxx> + +properties: + compatible: + const: intel,lgm-pcie + + device_type: + const: pci + + "#address-cells": + const: 3 + + "#size-cells": + const: 2 + + reg: + items: + - description: Controller control and status registers. + - description: PCIe configuration registers. + - description: Controller application registers. + + reg-names: + items: + - const: dbi + - const: config + - const: app + + ranges: + description: Ranges for the PCI memory and I/O regions. + + resets: + maxItems: 1 + + clocks: + description: PCIe registers interface clock. + + phys: + maxItems: 1 + + phy-names: + const: pciephy + + reset-gpios: + maxItems: 1 + + num-lanes: + description: Number of lanes to use for this port. + + linux,pci-domain: + $ref: /schemas/types.yaml#/definitions/uint32 + description: PCI domain ID. + + interrupts: + description: PCIe core integrated miscellaneous interrupt. + + '#interrupt-cells': + const: 1 + + interrupt-map-mask: + description: Standard PCI IRQ mapping properties. + + interrupt-map: + description: Standard PCI IRQ mapping properties. + + max-link-speed: + description: Specify PCI Gen for link capability. + + bus-range: + description: Range of bus numbers associated with this controller. + + reset-assert-ms: + description: | + Device reset interval in ms. + Some devices need an interval upto 500ms. By default it is 100ms. + +required: + - compatible + - device_type + - reg + - reg-names + - ranges + - resets + - clocks + - phys + - phy-names + - reset-gpios + - num-lanes + - linux,pci-domain + - interrupts + - interrupt-map + - interrupt-map-mask + +additionalProperties: false + +examples: + - | + pcie10:pcie@d0e00000 { + compatible = "intel,lgm-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = < + 0xd0e00000 0x1000 + 0xd2000000 0x800000 + 0xd0a41000 0x1000 + >; + reg-names = "dbi", "config", "app"; + linux,pci-domain = <0>; + max-link-speed = <4>; + bus-range = <0x00 0x08>; + interrupt-parent = <&ioapic1>; + interrupts = <67 1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &ioapic1 27 1>, + <0 0 0 2 &ioapic1 28 1>, + <0 0 0 3 &ioapic1 29 1>, + <0 0 0 4 &ioapic1 30 1>; + ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>; + resets = <&rcu0 0x50 0>; + clocks = <&cgu0 LGM_GCLK_PCIE10>; + phys = <&cb0phy0>; + phy-names = "pciephy"; + status = "okay"; + reset-assert-ms = <500>; + reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + num-lanes = <2>; + };
