On Wed, Aug 28, 2019 at 10:58:50PM +0530, Vidya Sagar wrote:
> Add 3.3V and 12V supplies regulators information of x16 PCIe slot in
> p2972-0000 platform which is owned by C5 controller and also enable C5
> controller.
>
> Signed-off-by: Vidya Sagar <vidyas@xxxxxxxxxx>
Reviewed-by: Andrew Murray <andrew.murray@xxxxxxx>
> ---
> V3:
> * None
>
> V2:
> * None
>
> .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 24 +++++++++++++++++++
> .../boot/dts/nvidia/tegra194-p2972-0000.dts | 4 +++-
> 2 files changed, 27 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
> index 62e07e1197cc..4c38426a6969 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
> @@ -289,5 +289,29 @@
> gpio = <&gpio TEGRA194_MAIN_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
> enable-active-high;
> };
> +
> + vdd_3v3_pcie: regulator@2 {
> + compatible = "regulator-fixed";
> + reg = <2>;
> +
> + regulator-name = "PEX_3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
> + regulator-boot-on;
> + enable-active-high;
> + };
> +
> + vdd_12v_pcie: regulator@3 {
> + compatible = "regulator-fixed";
> + reg = <3>;
> +
> + regulator-name = "VDD_12V";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + gpio = <&gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>;
> + regulator-boot-on;
> + enable-active-low;
> + };
> };
> };
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
> index 23597d53c9c9..d47cd8c4dd24 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
> +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
> @@ -93,9 +93,11 @@
> };
>
> pcie@141a0000 {
> - status = "disabled";
> + status = "okay";
>
> vddio-pex-ctl-supply = <&vdd_1v8ao>;
> + vpcie3v3-supply = <&vdd_3v3_pcie>;
> + vpcie12v-supply = <&vdd_12v_pcie>;
>
> phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
> <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
> --
> 2.17.1
>
