In subject: s/dt-bingings/dt-bindings/ Also, possibly s/PCI:/PCI: designware:/ since this only applies to designware-pcie.txt. On Mon, Aug 12, 2019 at 04:22:16AM +0000, Z.q. Hou wrote: > From: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx> > > The num-lanes is not a mandatory property, e.g. on FSL > Layerscape SoCs, the PCIe link training is completed > automatically base on the selected SerDes protocol, it > doesn't need the num-lanes to set-up the link width. > > It has been added in the Optional properties. This > patch is to remove it from the Required properties. > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx> > --- > Documentation/devicetree/bindings/pci/designware-pcie.txt | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt > index 5561a1c060d0..bd880df39a79 100644 > --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt > @@ -11,7 +11,6 @@ Required properties: > the ATU address space. > (The old way of getting the configuration address space from "ranges" > is deprecated and should be avoided.) > -- num-lanes: number of lanes to use > RC mode: > - #address-cells: set to <3> > - #size-cells: set to <2> > -- > 2.17.1 >
