On Tue, 2019-06-25 at 15:04 +0300, Mika Westerberg wrote: > > What's your experience in that area ? How (well) do they handle it in > > the boot firmware ? at least on arm64, boot firmwares are rather > > catastrophic when it comes to PCI, and on other embedded devices they > > are basically non-existent. > > Well my experience is quite limited to recent Macs and PCs which usually > handle the initial resource allocation just fine. In case of Thunderbolt > some "older" PCs handle everything in firmware, even the runtime > resource allocation via SMI handler accompanied with ACPI hotplug. So I'm tempted to toy a bit with the "realloc everything" platforms (all non-x86 embedded basically) use pci_bus_distribute_available_resources on the PCIe root ports unconditionally. I don't think it will be a problem with SR-IOV as I very much doubt you'll end up with a setup where we have under the root port SR-IOV devices that are *siblings* with a switch. If that ever becomes the case, SR-IOV should be hanlded somewhat as part of the add_list of the bus sizing anyway. I might do that as a test patch or behind a test config option, see how it goes, after I've consolidated all those platforms to go through the same generic code path, it will be a lot easier. I'm keen to limit that to PCIe root ports though, old stuff can stay as it is and die happily :) Cheers, Ben.
