On Fri, Apr 12, 2019 at 08:37:05AM +0000, Z.q. Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx>
>
> There are some 8-bit and 16-bit registers in PCIe
> configuration space, so add accessors for them.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx>
> Reviewed-by: Minghuan Lian <Minghuan.Lian@xxxxxxx>
> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@xxxxxxxxxxxxxx>
> ---
> V5:
> - Corrected and retouched the subject and changelog.
> - No functionality change.
>
> drivers/pci/controller/pcie-mobiveil.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
> index 411e9779da12..456adfee393c 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -268,11 +268,31 @@ static u32 csr_readl(struct mobiveil_pcie *pcie, u32 off)
> return csr_read(pcie, off, 0x4);
> }
>
> +static u32 csr_readw(struct mobiveil_pcie *pcie, u32 off)
> +{
> + return csr_read(pcie, off, 0x2);
> +}
> +
> +static u32 csr_readb(struct mobiveil_pcie *pcie, u32 off)
> +{
> + return csr_read(pcie, off, 0x1);
> +}
> +
> static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
> {
> csr_write(pcie, val, off, 0x4);
> }
>
> +static void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off)
> +{
> + csr_write(pcie, val, off, 0x2);
> +}
> +
> +static void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off)
> +{
> + csr_write(pcie, val, off, 0x1);
> +}
> +
They are not used so you should drop this patch.
Lorenzo
> static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
> {
> return (csr_readl(pcie, LTSSM_STATUS) &
> --
> 2.17.1
>
