On Wed, May 15, 2019 at 02:26:13PM -0500, Bjorn Helgaas wrote: > I should have forwarded this to the list earlier. Maybe somebody > wants to work on this? > > I *think* the problem is: > > - BIOS sets MTRR for 0x40_00000000-0x5f_ffffffff to be write-combining (WC) > - That covers part of this PCI aperture: root bus resource [mem > 0x40_00000000-0x7f_ffffffff window] > - That aperture includes a frame buffer: pci 0000:00:02.0: reg 0x18: > [mem 0x40_00000000-0x40_0fffffff 64bit pref] > - Linux assigned an LPSS BAR to the WC area: pci 0000:00:15.0: BAR > 0: assigned [mem 0x40_10000000-0x40_10000fff 64bit] > - The LPSS device doesn't work if MMIO accesses to it are combined via WC > > I'm not an x86/MTRR/PAT expert, but I think we should be able to make > this work correctly by changing that MTRR from WC to UC (I don't know > if there are BIOS/OS interface implications with this), or maybe using > PAT to override the MTRR WC setting to be UC for part or all of that > aperture. The frame buffer driver should be smart enough to request > WC if it wants it. The window for the PCI resources, provided by PCI Root Bridge, may be split to many parts as described by _CRS in ACPI, and BIOS should be consistent in providing both. I believe there is no issue with Linux in current state. Be "smart" here might give a downside(s) like reducing coverage to test exactly something as above BIOS issue. My 2 cents. -- With Best Regards, Andy Shevchenko
