Re: [PATCH 12/30] PCI: tegra: Add SW fixup for RAW violations

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On Fri, Apr 12, 2019 at 11:29:35AM +0530, Manikanta Maddireddy wrote:
> 
> On 12-Apr-19 1:31 AM, Bjorn Helgaas wrote:
> > On Thu, Apr 11, 2019 at 10:33:37PM +0530, Manikanta Maddireddy wrote:
> >> The logic which blocks read requests till AFI gets ACK for all outstanding
> >> MC writes does not behave correctly when number of outstanding write
> >> becomes more than 32 in Tegra124 and 132.
> >>
> >> SW fixup to prevent this issue is to limit outstanding posted writes and
> >> tweak updateFC timer threshold.
> >>
> >> Signed-off-by: Manikanta Maddireddy <mmaddireddy@xxxxxxxxxx>
> >>  static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
> >> @@ -2381,6 +2408,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
> >>  	.program_uphy = true,
> >>  	.update_clamp_threshold = false,
> >>  	.program_deskew_time = false,
> >> +	.raw_violation_fixup = false,
> >>  	.ectl.enable = false,
> > It doesn't really matter either way, but you don't *have* to
> > initialize all these flags to "false" since that's the default for
> > uninitialized fields in static structs like these.  If you left them
> > out, the structs would only contain the "true" items, and it'd be
> > easier to see what's special about each SoC.
> 
> SoC flags are explicitly set false if not supported, I am following
> same existing coding style in this driver. Maybe the intention here is
> to convey what is not supported by a particular SoC without going
> through soc struct definition.

Yes, this was originally done on purpose. I think it's good to follow
the existing convention, unless Bjorn feels strongly about it.

Thierry

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