On Fri, Feb 01, 2019 at 01:36:07PM +0800, honghui.zhang@xxxxxxxxxxxx wrote: > From: Honghui Zhang <honghui.zhang@xxxxxxxxxxxx> > > The PCIE_AXI_WINDOW0 defines the translate window size for the request > from EP side. Request outside of this window will be treated as > unsupported request. > > Enlarge this window size from fls(0xffffffff) to 2^33 to support 8GB > translate address range then EP DMA is capable of fully access 4GB > DRAM range(physical DRAM is start from 0x40000000). I have rewritten both patches logs with the aim of merging them even if it is quite late in the cycle, first you have to explain something to me. fls(0xffffffff) = 0x1f, which by your logic -> 2^31 What does it mean given what you say above ? That PCI devices can't do _any_ DMA in the current setting (given the DRAM start address) ? Lorenzo > Reported-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx> > Signed-off-by: Honghui Zhang <honghui.zhang@xxxxxxxxxxxx> > --- > drivers/pci/controller/pcie-mediatek.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c > index c42fe5c..0b6c728 100644 > --- a/drivers/pci/controller/pcie-mediatek.c > +++ b/drivers/pci/controller/pcie-mediatek.c > @@ -90,6 +90,12 @@ > #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0)) > #define PCIE_AXI_WINDOW0 0x448 > #define WIN_ENABLE BIT(7) > +/* > + * Define PCIe to AHB window size as 2^33 to support max 8GB address space > + * translate, support least 4GB DRAM size access from EP DMA(physical DRAM > + * start from 0x40000000). > + */ > +#define PCIE2AHB_SIZE 0x21 > > /* PCIe V2 configuration transaction header */ > #define PCIE_CFG_HEADER0 0x460 > @@ -713,7 +719,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) > writel(val, port->base + PCIE_AHB_TRANS_BASE0_H); > > /* Set PCIe to AXI translation memory space.*/ > - val = fls(0xffffffff) | WIN_ENABLE; > + val = PCIE2AHB_SIZE | WIN_ENABLE; > writel(val, port->base + PCIE_AXI_WINDOW0); > > return 0; > -- > 2.6.4 >
