On Wed, Jan 02, 2019 at 02:03:53PM +0800, honghui.zhang@xxxxxxxxxxxx wrote:
> From: Honghui Zhang <honghui.zhang@xxxxxxxxxxxx>
>
> drivers/pci/pcie-mediatek.c:720:13-16: WARNING: Suspicious code. resource_size is maybe missing with mem
>
> Generated by: scripts/coccinelle/api/resource_size.cocci
>
> Signed-off-by: Honghui Zhang <honghui.zhang@xxxxxxxxxxxx>
> ---
> drivers/pci/controller/pcie-mediatek.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
> index e307166..0168376 100644
> --- a/drivers/pci/controller/pcie-mediatek.c
> +++ b/drivers/pci/controller/pcie-mediatek.c
> @@ -654,7 +654,6 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
> struct resource *mem = &pcie->mem;
> const struct mtk_pcie_soc *soc = port->pcie->soc;
> u32 val;
> - size_t size;
> int err;
>
> /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
> @@ -706,8 +705,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
> mtk_pcie_enable_msi(port);
>
> /* Set AHB to PCIe translation windows */
> - size = mem->end - mem->start;
> - val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));
> + val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(resource_size(mem)));
> writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
>
> val = upper_32_bits(mem->start);
Unrelated to this patch, but just below this:
/* Set PCIe to AXI translation memory space.*/
val = fls(0xffffffff) | WIN_ENABLE;
writel(val, port->base + PCIE_AXI_WINDOW0);
Can you double-check the use of "fls(0xffffffff)"? That expression is
a constant and I think evaluates to 31 (0x1f), i.e.,
val = 0x1f | WIN_ENABLE;
I don't know the hardware, so this might be correct, but
"fls(0xffffffff)" looks funny because I think it's the same as
"fls(0x80000000)".
Bjorn
