Hi Gustavo,
On 1/11/2019 6:33 PM, Gustavo Pimentel wrote:
> Add support for the eDMA IP version 0 driver for both register maps (legacy
> and unroll).
>
> The legacy register mapping was the initial implementation, which consisted
> in having all registers belonging to channels multiplexed, which could be
> change anytime (which could led a race-condition) by view port register
> (access to only one channel available each time).
>
> This register mapping is not very effective and efficient in a multithread
> environment, which has led to the development of unroll registers mapping,
> which consists of having all channels registers accessible any time by
> spreading all channels registers by an offset between them.
>
> This version supports a maximum of 16 independent channels (8 write +
> 8 read), which can run simultaneously.
>
> Implements a scatter-gather transfer through a linked list, where the size
> of linked list depends on the allocated memory divided equally among all
> channels.
>
> Each linked list descriptor can transfer from 1 byte to 4 Gbytes and is
> alignmented to DWORD.
>
> Both SAR (Source Address Register) and DAR (Destination Address Register)
> are alignmented to byte.
>
> Changes:
> RFC v1->RFC v2:
> - Replace comments // (C99 style) by /**/
> - Replace magic numbers by defines
> - Replace boolean return from ternary operation by a double negation
> operation
> - Replace QWORD_HI/QWORD_LO macros by upper_32_bits()/lower_32_bits()
> - Fix the headers of the .c and .h files according to the most recent
> convention
> - Fix errors and checks pointed out by checkpatch with --strict option
> - Replace patch small description tag from dma by dmaengine
> - Refactor code to replace atomic_t by u32 variable type
> RFC v2->RFC v3:
> - Code rewrite to use FIELD_PREP() and FIELD_GET()
> - Add define to magic numbers
> - Fix minor bugs
>
> Signed-off-by: Gustavo Pimentel <gustavo.pimentel@xxxxxxxxxxxx>
> Cc: Vinod Koul <vkoul@xxxxxxxxxx>
> Cc: Dan Williams <dan.j.williams@xxxxxxxxx>
> Cc: Eugeniy Paltsev <paltsev@xxxxxxxxxxxx>
> Cc: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
> Cc: Russell King <rmk+kernel@xxxxxxxxxxxxxxx>
> Cc: Niklas Cassel <niklas.cassel@xxxxxxxxxx>
> Cc: Joao Pinto <jpinto@xxxxxxxxxxxx>
> Cc: Jose Abreu <jose.abreu@xxxxxxxxxxxx>
> Cc: Luis Oliveira <lolivei@xxxxxxxxxxxx>
> Cc: Vitor Soares <vitor.soares@xxxxxxxxxxxx>
> Cc: Nelson Costa <nelson.costa@xxxxxxxxxxxx>
> Cc: Pedro Sousa <pedrom.sousa@xxxxxxxxxxxx>
> +void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
> +{
> + struct dw_edma_chan *chan = chunk->chan;
> + struct dw_edma *dw = chan->chip->dw;
> + u32 tmp;
> + u64 llp;
> +
> + dw_edma_v0_core_write_chunk(chunk);
> +
> + if (first) {
> + /* Enable engine */
> + SET_RW(dw, chan->dir, engine_en, BIT(0));
> + /* Interrupt unmask - done, abort */
> + tmp = GET_RW(dw, chan->dir, int_mask);
> + tmp &= ~FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id));
> + tmp &= ~FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id));
> + SET_RW(dw, chan->dir, int_mask, tmp);
> + /* Linked list error */
> + tmp = GET_RW(dw, chan->dir, linked_list_err_en);
> + tmp |= FIELD_PREP(EDMA_V0_LINKED_LIST_ERR_MASK, BIT(chan->id));
> + SET_RW(dw, chan->dir, linked_list_err_en, tmp);
> + /* Channel control */
> + SET_CH(dw, chan->dir, chan->id, ch_control1,
> + (DW_EDMA_V0_CCS | DW_EDMA_V0_LLE));
> + /* Linked list - low, high */
> + llp = cpu_to_le64(chunk->ll_region.paddr);
> + SET_CH(dw, chan->dir, chan->id, llp_low, lower_32_bits(llp));
> + SET_CH(dw, chan->dir, chan->id, llp_high, upper_32_bits(llp));
> + }
> + /* Doorbell */
Not sure if DMA subsystem does this but maybe you need some kind
of barrier to ensure everything is coherent before granting
control to eDMA ?
> + SET_RW(dw, chan->dir, doorbell,
> + FIELD_PREP(EDMA_V0_DOORBELL_CH_MASK, chan->id));
> +}
> +
