A line might be used by the PCIe IP to reset the endpoint card upon:
- platform reset,
- hot reset,
- link failure.
Describe the properties needed in this case (optional).
Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx>
---
Documentation/devicetree/bindings/pci/aardvark-pci.txt | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/aardvark-pci.txt b/Documentation/devicetree/bindings/pci/aardvark-pci.txt
index a440f182ccf8..8b7f048705ec 100644
--- a/Documentation/devicetree/bindings/pci/aardvark-pci.txt
+++ b/Documentation/devicetree/bindings/pci/aardvark-pci.txt
@@ -24,6 +24,9 @@ contain the following properties:
The following are optional properties:
- phys: the PCIe PHY handle
+ - pinctrl-names: must be "default".
+ - pinctrl-0: pin control group to be used to mux the PCIe endpoint card
+ reset line so that it will be automatically driven by the PCIe IP.
In addition, the Device Tree describing an Aardvark PCIe controller
must include a sub-node that describes the legacy interrupt controller
@@ -55,6 +58,8 @@ Example:
<0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>;
phys = <&comphy1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_card_reset_pins &pcie_clkreq_pins>;
pcie_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
--
2.19.1
