Re: [PATCH v2] PCI: Block power management of certain ports with slot implemented bit set

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On Mon, Jan 7, 2019 at 2:01 PM Mika Westerberg
<mika.westerberg@xxxxxxxxxxxxxxx> wrote:
>
> Gigabyte X299 DESIGNARE EX motherboard has one PCIe root port that is
> connected to Alpine Ridge Thunderbolt controller. This port has slot
> implemented bit set in the config space but other than that it is not
> hotplug capable in the sense we are expecting in Linux (it has
> dev->is_hotplug_bridge set to 0):
>
> 00:1c.4 PCI bridge: Intel Corporation 200 Series PCH PCI Express Root Port #5
>         Bus: primary=00, secondary=05, subordinate=46, sec-latency=0
>         Memory behind bridge: 78000000-8fffffff [size=384M]
>         Prefetchable memory behind bridge: 00003800f8000000-00003800ffffffff [size=128M]
>         ...
>         Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
>         ...
>                 SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
>                         Slot #8, PowerLimit 25.000W; Interlock- NoCompl+
>                 SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
>                         Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
>                 SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock-
>                         Changed: MRL- PresDet+ LinkState+
>
> This system is using ACPI based hotplug to notify the OS that it needs
> to rescan the PCI bus (ACPI hotplug).
>
> If there is nothing connected to any of the Thunderbolt ports the root
> port will not have any runtime PM active children and is thus
> automatically runtime suspended pretty soon after boot by PCI PM core.
> Now, when a device is connected the BIOS SMI handler responsible for
> enumerating newly added devices is not able to find anything because the
> port is in D3.
>
> For this reason we block power management of PCIe root and downstream
> ports that have slot implemented set and have node in ACPI namespace.
>
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=202031
> Reported-by: Kedar A Dongre <kedar.a.dongre@xxxxxxxxx>
> Signed-off-by: Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx>

Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@xxxxxxxxx>

> ---
> Changes from v1:
>
>  - Block PM for all root and downstream ports with slot implemented bit set
>    and has an ACPI companion.
>
> The previous version can be found here:
>
>   https://patchwork.kernel.org/patch/10711553/
>
>  drivers/pci/pci.c | 18 +++++++++++++++++-
>  1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index c9d8e3c837de..04bdbcf1dfb7 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -2510,10 +2510,14 @@ void pci_config_pm_runtime_put(struct pci_dev *pdev)
>   */
>  bool pci_bridge_d3_possible(struct pci_dev *bridge)
>  {
> +       int type;
> +
>         if (!pci_is_pcie(bridge))
>                 return false;
>
> -       switch (pci_pcie_type(bridge)) {
> +       type = pci_pcie_type(bridge);
> +
> +       switch (type) {
>         case PCI_EXP_TYPE_ROOT_PORT:
>         case PCI_EXP_TYPE_UPSTREAM:
>         case PCI_EXP_TYPE_DOWNSTREAM:
> @@ -2546,6 +2550,18 @@ bool pci_bridge_d3_possible(struct pci_dev *bridge)
>                 if (bridge->is_hotplug_bridge)
>                         return false;
>
> +               /*
> +                * Some systems such as Gigabyte X299 the root port is
> +                * not marked hotplug capable but ACPI based hotplug is
> +                * still used to bring in the Thunderbolt controller. To
> +                * make sure those ports do not enter D3 and possibly
> +                * confuse the BIOS SMI handler, block D3 for them.
> +                */
> +               if (has_acpi_companion(&bridge->dev) &&
> +                   type != PCI_EXP_TYPE_UPSTREAM &&
> +                   pcie_caps_reg(bridge) & PCI_EXP_FLAGS_SLOT)
> +                       return false;
> +
>                 /*
>                  * It should be safe to put PCIe ports from 2015 or newer
>                  * to D3.
> --
> 2.19.2
>



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