Everyone: This series contains changes I made in order to enable support of PCIE IP block on i.MX8MQ SoCs. Changes since [v2], [fixes]: - Incorporated [patch] introducing drvdata - i.MX6 PHY operation gating converted to a single patch and to use a dedicated flag instead of doing explicit variant check - Kconfig entry changed to use ARM64 && ARCH_MXC - Dropped FALLTHROUGH annotations Changes since [v1]: - Driver changed to use single "fsl,controller-id" property to distinguish between two intances of PCIE IP block - All code pertaining to L1SS was dropped to simplify the patch - Documented additions to DT bindings Feedback is welcome! Thanks, Andrey Smirnov [patch] https://patchwork.kernel.org/patch/10712261/ [fixes] https://lore.kernel.org/linux-arm-kernel/20181216230916.22982-1-andrew.smirnov@xxxxxxxxx [v2] https://lore.kernel.org/linux-arm-kernel/20181206073545.10967-1-andrew.smirnov@xxxxxxxxx [v1] https://lore.kernel.org/linux-arm-kernel/20181117181225.10737-1-andrew.smirnov@xxxxxxxxx/ Andrey Smirnov (3): PCI: imx6: introduce drvdata PCI: imx6: Mark PHY functions as i.MX6 specific PCI: imx6: Add support for i.MX8MQ .../bindings/pci/fsl,imx6q-pcie.txt | 6 +- drivers/pci/controller/dwc/Kconfig | 4 +- drivers/pci/controller/dwc/pci-imx6.c | 150 +++++++++++++++--- 3 files changed, 136 insertions(+), 24 deletions(-) -- 2.19.1
