Re: [PATCH 0/3] PCI: designware: Fixing MSI handling flow

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On Mon, 2018-12-03 at 17:42 +0000, Lorenzo Pieralisi wrote:
> 
> 
> I need more testing done, I encourage other DWC maintainers to test my
> branch above. I am mulling over it but I may consider this v4.21
> material if I do not get enough testing done this week.

There's a far simpler patch with fewer side effects.  I still fail to
see why reverting the bug in < 4.21 and doing a proper series in 4.21
is so bad, vs keeping < 4.21 broken and doing a proper series in 4.21.

I think this series has flaws.

1. It doesn't address the keystone platform apparently disabling the
interrupt in what should be a mask.  Just running the ath10k driver
will not show this.  It will require something to actually mask the
interrupt at the dwc msi layer and observe that an MSI that arrives
while masked is lost on unmask.  And only keystone has a platform
method which does this.

2. It enables all MSIs on startup.  This will change the behavior if
something generates a MSI which has not been enabled.  That would not
be normal, but possibly an edge case with certain hardware coming out
of an soft-reset or power save.  Just running the ath10k driver is not
going to test this at all.

3. I am unconvinced the new lock in the irq ack fast path does anything
other than add additional irq latency.




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