On 11/26/18 4:09 PM, Stephen Warren wrote:
From: Stephen Warren <swarren@xxxxxxxxxx> Some implementations of the DWC PCIe endpoint controller do not allow access to DBI registers until the attached host has started REFCLK, released PERST, and the endpoint driver has initialized clocking of the DBI registers based on that. One such system is NVIDIA's T194 SoC. The PCIe endpoint subsystem and DWC driver currently don't work on such hardware, since they assume that all endpoint configuration can happen at any arbitrary time. Enhance the DWC endpoint driver to support such systems by caching all endpoint configuration in software, and only writing the configuration to hardware once it's been initialized. This is implemented by splitting all endpoint controller ops into two functions; the first which simply records/caches the desired configuration whenever called by the associated function driver and optionally calls the second, and the second which actually programs the configuration into hardware, which may be called either by the first function, or later when it's known that the DBI registers are available. Signed-off-by: Stephen Warren <swarren@xxxxxxxxxx> --- v2: Replace hw_regs_available with hw_regs_not_available. A 0 value in this field is now equivalent to the existing behaviour, so that drivers that allocate struct dw_pcie_ep with kzalloc or equivalent do not need to explicitly set this new field in order to maintain existing behaviour. Note: I have only compiled-tested this patch in the context of the mainline kernel since NVIDIA Tegra PCIe EP support is not yet present. However, I've built and tested an equivalent patch in our downstream kernel. I did have to manually port it to mainline due to conflicts though.
Any thoughts on this? Thanks.
