Hi Lorenzo, -----Original Message----- From: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx> Sent: 2018年11月30日 18:55 To: Xiaowei Bao <xiaowei.bao@xxxxxxx> Cc: bhelgaas@xxxxxxxxxx; robh+dt@xxxxxxxxxx; mark.rutland@xxxxxxx; shawnguo@xxxxxxxxxx; Leo Li <leoyang.li@xxxxxxx>; kishon@xxxxxx; arnd@xxxxxxxx; gregkh@xxxxxxxxxxxxxxxxxxx; M.h. Lian <minghuan.lian@xxxxxxx>; Mingkai Hu <mingkai.hu@xxxxxxx>; Roy Zang <roy.zang@xxxxxxx>; kstewart@xxxxxxxxxxxxxxxxxxx; cyrille.pitchen@xxxxxxxxxxxxxxxxxx; pombredanne@xxxxxxxx; shawn.lin@xxxxxxxxxxxxxx; niklas.cassel@xxxxxxxx; linux-pci@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linuxppc-dev@xxxxxxxxxxxxxxxx Subject: Re: [PATCHv2 3/6] PCI: layerscape: Add the EP mode support On Mon, Nov 05, 2018 at 04:46:50PM +0800, Xiaowei Bao wrote: > Add the EP mode support. > > Signed-off-by: Xiaowei Bao <xiaowei.bao@xxxxxxx> > --- > v2: > - Add the SoC specific compatibles. > > .../devicetree/bindings/pci/layerscape-pci.txt | 3 +++ > 1 files changed, 3 insertions(+), 0 deletions(-) Wrong commit $SUBJECT, this is not PCI code, it is a DT binding update, I will have a look at the rest of the series to see if I can update this patch or you will do it with the next respin. Lorenzo [Xiaowei Bao] HI Lorenzo, thanks a lot, I will send V3 patch to modify the commits. > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > index 66df1e8..9c090c7 100644 > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > @@ -13,12 +13,15 @@ information. > > Required properties: > - compatible: should contain the platform identifier such as: > + RC mode: > "fsl,ls1021a-pcie", "snps,dw-pcie" > "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie" > "fsl,ls2088a-pcie" > "fsl,ls1088a-pcie" > "fsl,ls1046a-pcie" > "fsl,ls1012a-pcie" > + EP mode: > + "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep" > - reg: base addresses and lengths of the PCIe controller register blocks. > - interrupts: A list of interrupt outputs of the controller. Must contain an > entry for each entry in the interrupt-names property. > -- > 1.7.1 >
