From: Stephen Warren <swarren@xxxxxxxxxx>
The DWC PCIe core contains various separate register spaces: DBI,
DBI2,
ATU, DMA, etc. The relationship between the addresses of these
register
spaces is entirely determined by the implementation of the IP
block, not
by the IP block design itself. Hence, the DWC driver must not make
assumptions that one register space can be accessed at a fixed
offset from
any other register space. To avoid such assumptions, introduce an
explicit/separate register pointer for the ATU register space. In
particular, the current assumption is not valid for NVIDIA's T194
SoC.
The ATU register space is only used on systems that require
unrolled ATU
access. This property is detected at run-time for host
controllers, and
when this is detected, this patch provides a default value for
atu_base
that matches the previous assumption re: register layout. An
alternative
would be to update all drivers for HW that requires unrolled
access to
explicitly set atu_base. However, it's hard to tell which drivers
would
require atu_base to be set. The unrolled property is not detected for
endpoint systems, and so any endpoint driver that requires
unrolled access
must explicitly set the iatu_unroll_enabled flag (none do at
present), and
so a check is added to require the driver to also set atu_base
while at
it.
Signed-off-by: Stephen Warren <swarren@xxxxxxxxxx>
Acked-by: Gustavo Pimentel <gustavo.pimentel@xxxxxxxxxxxx>
---
v2:
* Modified patch subject
* Added missing outer brackets to PCIE_GET_ATU_INB_UNR_REG_OFFSET
macro
---
.../pci/controller/dwc/pcie-designware-ep.c | 4 ++++
.../pci/controller/dwc/pcie-designware-host.c | 3 +++
drivers/pci/controller/dwc/pcie-designware.c | 8 ++++----
drivers/pci/controller/dwc/pcie-designware.h | 20
+++++++++++++++----
4 files changed, 27 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c
b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 1e7b02221eac..880210366e71 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -504,6 +504,10 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
dev_err(dev, "dbi_base/dbi_base2 is not populated\n");
return -EINVAL;
}
+ if (pci->iatu_unroll_enabled && !pci->atu_base) {
+ dev_err(dev, "atu_base is not populated\n");
+ return -EINVAL;
+ }
ret = of_property_read_u32(np, "num-ib-windows",
&ep->num_ib_windows);
if (ret < 0) {
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c
b/drivers/pci/controller/dwc/pcie-designware-host.c
index 29a05759a294..2ebb7f4768cf 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -699,6 +699,9 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
dev_dbg(pci->dev, "iATU unroll: %s\n",
pci->iatu_unroll_enabled ? "enabled" : "disabled");
